Patents by Inventor Hui Hua LEE
Hui Hua LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240126816Abstract: Herein is database query acceleration from dynamic discovery of whether contents of a persistent column can be stored in an accelerated representation in storage-side memory. In an embodiment, based on data type discovery, a storage server detects that column values in a persistent column have a particular data type. Based on storage-side metadata including a frequency of access of the persistent column as an offload input column for offload computation requests on a certain range of memory addresses, the storage server autonomously decides to generate and store, in storage-side memory in the storage server, an accelerated representation of the persistent column that is based on the particular data type. The storage server receives a request to perform an offload computation for the offload input column. Based on the accelerated representation of the persistent column, execution of the offload computation is accelerated.Type: ApplicationFiled: September 29, 2023Publication date: April 18, 2024Inventors: Jorge Luis Issa Garcia, Teck Hua Lee, Sheldon Andre Kevin Lewis, Bangalore Prashanth, Hui Joe Chang, Zhen Hua Liu, Aurosish Mishra, Shasank K. Chavan
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Patent number: 11728252Abstract: A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material.Type: GrantFiled: April 10, 2020Date of Patent: August 15, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hui Hua Lee, Chun Hao Chiu, Hui-Ying Hsieh, Kuo-Hua Chen, Chi-Tsung Chiu
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Patent number: 11127707Abstract: A semiconductor package structure includes a base material, at least one semiconductor chip, an encapsulant, a depression structure, a redistribution layer and at least one conductive via. The semiconductor chip is disposed on the base material. The encapsulant is disposed on the base material and covers the at least one semiconductor chip. The encapsulant has an outer side surface. The depression structure is disposed adjacent to and exposed from of the outer side surface the encapsulant. The redistribution layer is disposed on the encapsulant. The conductive via is disposed in the encapsulant and electrically connects the semiconductor chip and the redistribution layer.Type: GrantFiled: July 15, 2019Date of Patent: September 21, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chi-Tsung Chiu, Hui-Ying Hsieh, Hui Hua Lee, Cheng Yuan Chen
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Patent number: 11037868Abstract: A semiconductor device package includes a metal carrier, a passive device, a conductive adhesive material, a dielectric layer and a conductive via. The metal carrier has a first conductive pad and a second conductive pad spaced apart from the first conductive pad. The first conductive pad and the second conductive pad define a space therebetween. The passive device is disposed on top surfaces of first conductive pad and the second conductive pad. The conductive adhesive material electrically connects a first conductive contact and a second conductive contact of the passive device to the first conductive pad and the second conductive pad respectively. The dielectric layer covers the metal carrier and the passive device and exposes a bottom surface of the first conductive pad and the second conductive pad. The conductive via extends within the dielectric layer and is electrically connected to the first conductive pad and/or the second conductive pad.Type: GrantFiled: February 25, 2020Date of Patent: June 15, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hui Hua Lee, Hui-Ying Hsieh, Cheng-Hung Ko, Chi-Tsung Chiu
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Publication number: 20210020594Abstract: A semiconductor package structure includes a base material, at least one semiconductor chip, an encapsulant, a depression structure, a redistribution layer and at least one conductive via. The semiconductor chip is disposed on the base material. The encapsulant is disposed on the base material and covers the at least one semiconductor chip. The encapsulant has an outer side surface. The depression structure is disposed adjacent to and exposed from of the outer side surface the encapsulant. The redistribution layer is disposed on the encapsulant. The conductive via is disposed in the encapsulant and electrically connects the semiconductor chip and the redistribution layer.Type: ApplicationFiled: July 15, 2019Publication date: January 21, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chi-Tsung CHIU, Hui-Ying HSIEH, Hui Hua LEE, Cheng Yuan CHEN
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Publication number: 20200243427Abstract: A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material.Type: ApplicationFiled: April 10, 2020Publication date: July 30, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hui Hua LEE, Chun Hao CHIU, Hui-Ying Hsieh, Kuo-Hua CHEN, Chi-Tsung CHIU
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Patent number: 10707157Abstract: A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material.Type: GrantFiled: June 13, 2017Date of Patent: July 7, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hui Hua Lee, Chun Hao Chiu, Hui-Ying Hsieh, Kuo-Hua Chen, Chi-Tsung Chiu
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Publication number: 20200194327Abstract: A semiconductor device package includes: (1) a conductive base comprising a sidewall, a cavity defined from a first surface of the conductive base, the cavity having a bottom surface and a depth; (2) a semiconductor die disposed on the bottom surface of the cavity, the semiconductor die having a first surface and a second surface opposite the first surface, the second surface of the semiconductor die bonded to the bottom surface of the cavity; and (3) a first insulating material covering the sidewall of the conductive base and extending to a bottom surface of the conductive base.Type: ApplicationFiled: February 26, 2020Publication date: June 18, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chi-Tsung CHIU, Meng-Jen WANG, Cheng-Hsi CHUANG, Hui-Ying HSIEH, Hui Hua LEE
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Publication number: 20200194356Abstract: A semiconductor device package includes a metal carrier, a passive device, a conductive adhesive material, a dielectric layer and a conductive via. The metal carrier has a first conductive pad and a second conductive pad spaced apart from the first conductive pad. The first conductive pad and the second conductive pad define a space therebetween. The passive device is disposed on top surfaces of first conductive pad and the second conductive pad. The conductive adhesive material electrically connects a first conductive contact and a second conductive contact of the passive device to the first conductive pad and the second conductive pad respectively. The dielectric layer covers the metal carrier and the passive device and exposes a bottom surface of the first conductive pad and the second conductive pad. The conductive via extends within the dielectric layer and is electrically connected to the first conductive pad and/or the second conductive pad.Type: ApplicationFiled: February 25, 2020Publication date: June 18, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hui Hua LEE, Hui-Ying HSIEH, Cheng-Hung KO, Chi-Tsung CHIU
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Patent number: 10615105Abstract: A semiconductor device package includes a metal carrier, a passive device, a conductive adhesive material, a dielectric layer and a conductive via. The metal carrier has a first conductive pad and a second conductive pad spaced apart from the first conductive pad. The first conductive pad and the second conductive pad define a space therebetween. The passive device is disposed on top surfaces of first conductive pad and the second conductive pad. The conductive adhesive material electrically connects a first conductive contact and a second conductive contact of the passive device to the first conductive pad and the second conductive pad respectively. The dielectric layer covers the metal carrier and the passive device and exposes a bottom surface of the first conductive pad and the second conductive pad. The conductive via extends within the dielectric layer and is electrically connected to the first conductive pad and/or the second conductive pad.Type: GrantFiled: October 10, 2018Date of Patent: April 7, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hui Hua Lee, Hui-Ying Hsieh, Cheng-Hung Ko, Chi-Tsung Chiu
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Publication number: 20190122969Abstract: A semiconductor device package includes a metal carrier, a passive device, a conductive adhesive material, a dielectric layer and a conductive via. The metal carrier has a first conductive pad and a second conductive pad spaced apart from the first conductive pad. The first conductive pad and the second conductive pad define a space therebetween. The passive device is disposed on top surfaces of first conductive pad and the second conductive pad. The conductive adhesive material electrically connects a first conductive contact and a second conductive contact of the passive device to the first conductive pad and the second conductive pad respectively. The dielectric layer covers the metal carrier and the passive device and exposes a bottom surface of the first conductive pad and the second conductive pad. The conductive via extends within the dielectric layer and is electrically connected to the first conductive pad and/or the second conductive pad.Type: ApplicationFiled: October 10, 2018Publication date: April 25, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hui Hua LEE, Hui-Ying HSIEH, Cheng-Hung KO, Chi-Tsung CHIU
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Publication number: 20180358276Abstract: A semiconductor device package includes: (1) a conductive base comprising a sidewall, a cavity defined from a first surface of the conductive base, the cavity having a bottom surface and a depth; (2) a semiconductor die disposed on the bottom surface of the cavity, the semiconductor die having a first surface and a second surface opposite the first surface, the second surface of the semiconductor die bonded to the bottom surface of the cavity; and (3) a first insulating material covering the sidewall of the conductive base and extending to a bottom surface of the conductive base.Type: ApplicationFiled: August 21, 2018Publication date: December 13, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chi-Tsung CHIU, Meng-Jen WANG, Cheng-Hsi CHUANG, Hui-Ying HSIEH, Hui Hua LEE
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Patent number: 10083888Abstract: A semiconductor device package includes a conductive base, and a cavity defined from a first surface of the conductive base, the cavity having a bottom surface and a depth. A semiconductor die is disposed on the bottom surface of the cavity, the semiconductor die having a first surface and a second surface opposite the first surface. The second surface of the semiconductor die is bonded to the bottom surface of the cavity. A distance between the first surface of the semiconductor die and the first surface of the conductive base is about 20% of the depth of the cavity.Type: GrantFiled: August 29, 2016Date of Patent: September 25, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chi-Tsung Chiu, Meng-Jen Wang, Cheng-Hsi Chuang, Hui-Ying Hsieh, Hui Hua Lee
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Patent number: 9991193Abstract: A semiconductor device package includes a first conductive base, a first semiconductor die, a dielectric layer, a first patterned conductive layer, and a second patterned conductive layer. The first conductive base defines a first cavity. The first semiconductor die is on a bottom surface of the first cavity. The dielectric layer covers the first semiconductor die, the first surface and the second surface of the first conductive base and fills the first cavity. The first patterned conductive layer is on a first surface of the dielectric layer. The second patterned conductive layer is on a second surface of the dielectric layer.Type: GrantFiled: June 13, 2017Date of Patent: June 5, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Kay Stefan Essig, Chi-Tsung Chiu, Hui Hua Lee
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Publication number: 20170365543Abstract: A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material.Type: ApplicationFiled: June 13, 2017Publication date: December 21, 2017Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hui Hua LEE, Chun Hao CHIU, Hui-Ying Hsieh, Kuo-Hua CHEN, Chi-Tsung CHIU
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Publication number: 20170365542Abstract: A semiconductor device package includes a first conductive base, a first semiconductor die, a dielectric layer, a first patterned conductive layer, and a second patterned conductive layer. The first conductive base defines a first cavity. The first semiconductor die is on a bottom surface of the first cavity. The dielectric layer covers the first semiconductor die, the first surface and the second surface of the first conductive base and fills the first cavity. The first patterned conductive layer is on a first surface of the dielectric layer. The second patterned conductive layer is on a second surface of the dielectric layer.Type: ApplicationFiled: June 13, 2017Publication date: December 21, 2017Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Kay Stefan ESSIG, Chi-Tsung CHIU, Hui Hua LEE
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Publication number: 20170148746Abstract: A semiconductor device package includes a conductive base, and a cavity defined from a first surface of the conductive base, the cavity having a bottom surface and a depth. A semiconductor die is disposed on the bottom surface of the cavity, the semiconductor die having a first surface and a second surface opposite the first surface. The second surface of the semiconductor die is bonded to the bottom surface of the cavity. A distance between the first surface of the semiconductor die and the first surface of the conductive base is about 20% of the depth of the cavity.Type: ApplicationFiled: August 29, 2016Publication date: May 25, 2017Inventors: Chi-Tsung CHIU, Meng-Jen WANG, Cheng-Hsi CHUANG, Hui-Ying HSIEH, Hui Hua LEE