Patents by Inventor Huilin Chang

Huilin Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit device
    Patent number: 8324731
    Abstract: An integrated circuit device having at least a bond pad for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions of the first passivation layer, having a first portion overlying the first passivation layer and a second portion overlying the openings. A second passivation layer overlies the first passivation layer and covers edges of the conductive layer.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: December 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Shwang-Ming Jeng, Yung-Cheng Lu, Huilin Chang, Ting-Yu Shen, Yichi Liao
  • Integrated circuit device
    Publication number: 20100065969
    Abstract: An integrated circuit device having at least a bond pad for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions of the first passivation layer, having a first portion overlying the first passivation layer and a second portion overlying the openings. A second passivation layer overlies the first passivation layer and covers edges of the conductive layer.
    Type: Application
    Filed: November 23, 2009
    Publication date: March 18, 2010
    Inventors: Chen-Hua Yu, Shwang-Ming Jeng, Yung-Cheng Lu, Huilin Chang, Ting-Yu Shen, Yichi Liao
  • Bond pads and methods for fabricating the same
    Patent number: 7646097
    Abstract: Bond pads for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions of the first passivation layer, having a first portion overlying the first passivation layer and a second portion overlying the openings. A second passivation layer overlies the first passivation layer and covers edges of the conductive layer.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: January 12, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Shwang-Ming Jeng, Yung-Cheng Lu, Huilin Chang, Ting-Yu Shen, Yichi Liao
  • SELF-ALIGNED DIELECTRIC CAP
    Publication number: 20080280449
    Abstract: A method of forming a dielectric layer includes providing a substrate that has a copper region and a non-copper region. The substrate is etched to remove any copper oxides from the copper region. A dielectric cap is then selectively formed over the copper region of the substrate so that little or no dielectric cap is formed over the non-copper region of the substrate.
    Type: Application
    Filed: May 10, 2007
    Publication date: November 13, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huilin Chang, Yung-Cheng Lu, Syun-Ming Jang
  • Bond pads and methods for fabricating the same
    Publication number: 20070080460
    Abstract: Bond pads for semiconductor devices and method for fabricating the same are provided. A bond pad has a first passivation layer having a plurality of openings. A conductive layer which overlies the openings and portions of the first passivation layer, having a first portion overlying the first passivation layer and a second portion overlying the openings. A second passivation layer overlies the first passivation layer and covers edges of the conductive layer.
    Type: Application
    Filed: October 11, 2005
    Publication date: April 12, 2007
    Inventors: Chen-Hua Yu, Shwang-Ming Jeng, Yung-Cheng Lu, Huilin Chang, Ting-Yu Shen, Yichi Liao
  • Integrated treatment method for obtaining robust low dielectric constant materials
    Patent number: 7071093
    Abstract: An integrated method comprises providing a low dielectric material, applying a first treatment altering a first property of the low dielectric material, and applying a second treatment altering a second property of the treated low dielectric material and producing a lower dielectric material with better mechanical stability.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: July 4, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mong-Song Liang, Yung-Cheng Lu, Huilin Chang
  • Integrated treatment method for obtaining robust low dielectric constant materials
    Publication number: 20050215052
    Abstract: An integrated method comprises providing a low dielectric material, applying a first treatment altering a first property of the low dielectric material, and applying a second treatment altering a second property of the treated low dielectric material and producing a lower dielectric material with better mechanical stability.
    Type: Application
    Filed: March 26, 2004
    Publication date: September 29, 2005
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mong-Song Liang, Yung-Cheng Lu, Huilin Chang