Patents by Inventor Hui-Yu Lee

Hui-Yu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140103545
    Abstract: A method of generating masks for making an integrated circuit includes determining if a coupling capacitance value of a conductive path of a first and second groups of conductive paths of the integrated circuit is greater than a predetermined threshold value. The determination is performed based on at least a resistance-capacitance extraction result of the conductive path and a predetermined level of mask misalignment. The layout patterns are modified to increase an overall vertical distance between the first group of conductive paths and the second group of conductive paths if the coupling capacitance value is greater than the predetermined threshold value.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 17, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui Yu LEE, Feng Wei KUO, Jui-Feng KUAN, Yi-Kan CHENG
  • Patent number: 8701055
    Abstract: The present disclosure provides a system and method of designing an integrated circuit. A plurality of devices are selected and properties assigned to each of the plurality of devices. These plural devices having assigned properties are then combined into a macro cell whereby a density gradient pattern is generated for the macro cell. Layout dependent effect (LDE) parameters are determined for the macro cell as a function of the combination of plural devices, and electrical performance characteristics for the macro cell are simulated. A layout distribution of the plurality of devices within the macro cell can then be determined as a function of one or more of the simulated electrical performance characteristics, determined LDE parameters, and generated density gradient pattern. A design layout of an integrated circuit can be generated corresponding to the layout distribution for the macro cell.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: April 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui Yu Lee, Chi-Wen Chang, Jui-Feng Kuan, Wen-Shen Chou
  • Publication number: 20140001609
    Abstract: Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.
    Type: Application
    Filed: September 5, 2013
    Publication date: January 2, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng-Wei KUO, Hui Yu LEE, Huan-Neng CHEN, Yen-Jen CHEN, Yu-Ling LIN, Chewn-Pu JOU
  • Patent number: 8621409
    Abstract: A method includes extracting a first netlist from a first layout of a semiconductor circuit and estimating layout-dependent effect data based on the first netlist. A first simulation of the semiconductor circuit is performed based on the first netlist using an electronic design automation tool, and a second simulation of the semiconductor circuit is performed based on a circuit schematic using the electronic design automation tool. A weight and a sensitivity of the at least one layout-dependent effect are calculated, and the first layout of the semiconductor circuit is adjusted based on the weight and the sensitivity to provide a second layout of the semiconductor circuit. The second layout is stored in a non-transient storage medium.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: December 31, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui Yu Lee, Feng Wei Kuo, Ching-Shun Yang, Yi-Kan Cheng, Jui-Feng Kuan
  • Publication number: 20130298091
    Abstract: A method of generating a circuit layout of an integrated circuit includes generating layout geometry parameters for at least a predetermined portion of an original netlist of the integrated circuit. A consolidated netlist including information from the original netlist and the layout geometry parameters is generated. Then, the circuit layout is generated based on the consolidated netlist.
    Type: Application
    Filed: May 4, 2012
    Publication date: November 7, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui Yu LEE, Feng Wei KUO, Jui-Feng KUAN, Simon Yi-Hung CHEN
  • Publication number: 20130290916
    Abstract: A method includes extracting a first netlist from a first layout of a semiconductor circuit and estimating layout-dependent effect data based on the first netlist. A first simulation of the semiconductor circuit is performed based on the first netlist using an electronic design automation tool, and a second simulation of the semiconductor circuit is performed based on a circuit schematic using the electronic design automation tool. A weight and a sensitivity of the at least one layout-dependent effect are calculated, and the first layout of the semiconductor circuit is adjusted based on the weight and the sensitivity to provide a second layout of the semiconductor circuit. The second layout is stored in a non-transient storage medium.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui Yu LEE, Feng Wei KUO, Ching-Shun YANG, Yi-Kan CHENG, Jui-Feng KUAN
  • Publication number: 20130134553
    Abstract: Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.
    Type: Application
    Filed: January 30, 2012
    Publication date: May 30, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Feng Wei Kuo, Hui Yu Lee, Huan-Neng Chen, Yen-Jen Chen, Yu-Ling Lin, Chewn-Pu Jou
  • Patent number: 8073825
    Abstract: A data correction apparatus, a data correction method and a tangible machine-readable medium thereof are provided. The data correction method comprises the following steps: receiving a plurality of packets; determining that all of the packets are erroneous packets according to cyclic redundancy check (CRC) information thereof; retrieving any number of pairs among the packets to proceed an exclusive-OR (XOR) logical calculation to generate a plurality of error patterns; obtaining an overall error pattern according to an OR logical calculation of the error patterns; and calculating a correct packet according to one or more of the packets and the overall error pattern.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: December 6, 2011
    Assignee: Institute for Information Industry
    Inventors: Shiann-Tsong Sheu, Tsung-Yu Tsai, Kai-Fang Cheng, Chih Sheng Chang, Hui-Yu Lee
  • Publication number: 20110227689
    Abstract: A method for fabricating an inductor structure having an increased quality factor (Q) is provided. In one embodiment, a substrate is provided and a plurality of metal layers are formed on the substrate. A spirally patterned conductor layer is formed over and in the substrate and in the metal layers to produce a planar spiral inductor. A via hole is formed over and in the substrate and in the metal layers within the spirally patterned conductor layer, the via hole being formed by a through silicon via (TSV) process. Thereafter, the via hole is filled with a core layer, wherein the core layer extends from a bottom surface of the substrate to a top surface of the metal layers.
    Type: Application
    Filed: May 6, 2011
    Publication date: September 22, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Cheng Chang, Hui-Yu Lee
  • Publication number: 20100153817
    Abstract: A data correction apparatus, a data correction method and a tangible machine-readable medium thereof are provided. The data correction method comprises the following steps: receiving a plurality of packets; determining that all of the packets are erroneous packets according to cyclic redundancy check (CRC) information thereof; retrieving any number of pairs among the packets to proceed an exclusive-OR (XOR) logical calculation to generate a plurality of error patterns; obtaining an overall error pattern according to an OR logical calculation of the error patterns; and calculating a correct packet according to one or more of the packets and the overall error pattern.
    Type: Application
    Filed: June 17, 2009
    Publication date: June 17, 2010
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Shiann-Tsong SHEU, Tsung-Yu TSAI, Kai-Fang CHENG, Chih Sheng CHANG, Hui-Yu LEE
  • Publication number: 20090140383
    Abstract: A method for fabricating an inductor structure having an increased quality factor (Q) is provided. In one embodiment, a substrate is provided over which a spirally patterned conductor layer is formed to produce a planar spiral inductor. A via hole is formed in the substrate within the spirally patterned conductor layer, the via hole being formed by through silicon via (TSV). Thereafter, the via hole is filled with a core layer, wherein the core layer extends from a bottom surface of the substrate to a top surface thereof.
    Type: Application
    Filed: November 29, 2007
    Publication date: June 4, 2009
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Cheng Chang, Hui-Yu Lee