Patents by Inventor Hui Zang

Hui Zang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200335594
    Abstract: Structures for field effect-transistors and methods of forming field-effect transistors. A gate structure includes a gate electrode and a gate dielectric layer that are arranged between a first sidewall spacer and a second sidewall spacer. The gate structure has a top surface that is recessed relative to the first and second sidewall spacers. A gate cap is arranged over a section of the gate structure and over the first and sidewall spacers. The gate cap has a first section of a first width arranged over the section of the gate structure and a second section of a second width arranged over the section of the gate cap, the first sidewall spacer, and the second sidewall spacer. A dielectric liner is arranged between the gate cap and the gate structure, between the gate cap and the first sidewall spacer, and between the gate cap and the second sidewall spacer.
    Type: Application
    Filed: April 17, 2019
    Publication date: October 22, 2020
    Inventors: Hui Zang, Shesh Mani Pandey
  • Publication number: 20200335619
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line gate structures and methods of manufacture. The structure includes: a plurality of adjacent gate structures; a bridged gate structure composed of a plurality of the adjacent gate structures; source and drain regions adjacent to the bridged gate structure and comprising source and drain metallization features; and contacts to the bridged gate structure and the source and drain metallization features.
    Type: Application
    Filed: April 17, 2019
    Publication date: October 22, 2020
    Inventors: Yanping SHEN, Haiting WANG, Hui ZANG, Jiehui SHU
  • Publication number: 20200335600
    Abstract: Disclosed is a transistor that includes a sidewall spacer positioned adjacent a sidewall of a gate structure, wherein the sidewall spacer comprises a notch proximate the lower end and wherein the notch is defined by a substantially vertically oriented side surface and a substantially horizontally oriented upper surface. An epi cavity in the substrate includes a substantially vertically oriented cavity sidewall that is substantially vertically aligned with the substantially vertically oriented side surface of the notch and an epi semiconductor material positioned in the epi cavity and in the notch, wherein the epi semiconductor material contacts and engages the substantially vertically oriented side surface of the notch and the substantially horizontally oriented upper surface of the notch.
    Type: Application
    Filed: April 16, 2019
    Publication date: October 22, 2020
    Inventors: Yanping Shen, Jiehui Shu, Hui Zang
  • Publication number: 20200335435
    Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.
    Type: Application
    Filed: July 1, 2020
    Publication date: October 22, 2020
    Inventors: Jiehui Shu, Xiaoqiang Zhang, Haizhou Yin, Moosung M. Chae, Jinping Liu, Hui Zang
  • Patent number: 10811319
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures; source and drain regions adjacent to respective gate structures of the plurality of gate structures; metallization features contacting selected source and drain regions; and recessed metallization features contacting other selected source and drain regions.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: October 20, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie
  • Patent number: 10811409
    Abstract: Methods of manufacturing FinFETs including providing a precursor FinFET structure having a substrate with fins thereon, S/D junctions on fin tops, an STI layer on the substrate and between fins, a conformal first dielectric layer on the STI layer and S/D junctions, and a second dielectric layer on the first dielectric layer; forming a conformal third dielectric layer on the second dielectric layer and surfaces of the first dielectric layer located above the second dielectric layer; forming a fourth dielectric layer on the third dielectric layer such that third dielectric layer located between adjacent fins is exposed and such that third dielectric layer located above the adjacent fins is exposed; removing the exposed third dielectric layer and the first dielectric layer located thereunder, thereby exposing the S/D junctions; and forming a metal contact on the exposed S/D junctions and the exposed portion of the third dielectric layer between adjacent fins.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: October 20, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Hui Zang, Guowei Xu, Jian Gao
  • Patent number: 10811422
    Abstract: Methods according to the disclosure include forming a mask over a substrate to cover a first semiconductor region on the substrate and a first gate structure on the first semiconductor region. The second semiconductor region may be recessed from an initial height above the substrate to a reduced height above the substrate. The mask may be removed before forming a plurality of cavities by etching the first and second semiconductor regions, the plurality of cavities including a first cavity having a first depth within the first semiconductor region and a second cavity having a second depth within the second semiconductor region, wherein the second depth is greater than the first depth. The method also may include forming a plurality of epitaxial regions within the plurality of cavities.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: October 20, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yanping Shen, Wei Hong, Hui Zang, David P. Brunco
  • Patent number: 10804379
    Abstract: A method for producing a finFET to prevent gate contact and trench silicide (TS) electrical shorts. Embodiments include forming a finFET over a substrate, the finFET comprising an epi S/D region formed at sides of a gate; forming an ?-Si layer in a recess over the epi S/D; forming an oxide layer over the ?-Si layer; forming a non-TS isolation opening over the substrate; forming a low dielectric constant layer in the non-TS isolation opening; removing the oxide layer and ?-Si layer; forming an opening over the gate and an opening over the epi S/D region; and forming a gate contact in the opening over the gate and an epi S/D contact over the opening over the epi S/D region.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: October 13, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Scott Beasor
  • Patent number: 10797046
    Abstract: Embodiments of the disclosure provide a resistor structure for an integrated circuit (IC) and related methods. The resistor structure may include: a shallow trench isolation (STI) region on a substrate; a resistive material above a portion of the shallow trench isolation (STI) region; a gate structure on another portion of the STI region, above the substrate, and horizontally displaced from the resistive material; an insulative barrier above the STI region and contacting an upper surface and sidewalls of the resistive material, an upper surface of the insulative barrier being substantially coplanar with an upper surface of the gate structure; and a pair of contacts within the insulative barrier, and each positioned on an upper surface of the resistive material.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Jiehui Shu, Hui Zang
  • Patent number: 10797049
    Abstract: A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Haiting Wang, Chung Foong Tan, Guowei Xu, Ruilong Xie, Scott H. Beasor, Liu Jiang
  • Publication number: 20200312775
    Abstract: A semiconductor device structure is provided that includes a dielectric layer and a barrier layer having at least two layers of two dimensional materials on the dielectric layer, wherein each layer is made of a different two dimensional material.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: RINUS TEK PO LEE, FUAD AL-AMOODY, ASLI SIRMAN, JOSEPH KYALO KASSIM, HUI ZANG, BHARAT V. KRISHNAN
  • Publication number: 20200312947
    Abstract: Embodiments of the disclosure provide a resistor structure for an integrated circuit (IC) and related methods.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Jiehui Shu, Hui Zang
  • Publication number: 20200312718
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures; a plurality of gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of gate structures; a single diffusion break between the diffusion regions of the adjacent gate structures; and a liner separating the single diffusion break from the diffusion regions.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Hui ZANG, Ruilong XIE
  • Patent number: 10790363
    Abstract: The disclosure relates to methods of forming integrated circuit (IC) structures with a metal cap on a cobalt layer for source and drain regions of a transistor. An integrated circuit (IC) structure according to the disclosure may include: a semiconductor fin on a substrate; a gate structure over the substrate, the gate structure having a first portion extending transversely across the semiconductor fin; an insulator cap positioned on the gate structure above the semiconductor fin; a cobalt (Co) layer on the semiconductor fin adjacent to the gate structure, wherein an upper surface of the Co layer is below an upper surface of the gate structure; and a metal cap on the Co layer.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: September 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Laertis Economikos, Kevin J. Ryan, Ruilong Xie, Hui Zang
  • Publication number: 20200303261
    Abstract: A method of forming an IC structure includes providing a metal gate structure, a spacer adjacent the metal gate structure and a contact to each of a pair of source/drain regions adjacent sides of the spacer. The spacer includes a first dielectric having a first dielectric constant. The metal gate structure is recessed, and the spacer is recessed to have an upper surface of the first dielectric below an upper surface of the metal gate structure, leaving a lower spacer portion. An upper spacer portion of a second dielectric having a dielectric constant lower than the first dielectric is formed over the lower spacer portion. A gate cap is formed over the metal gate structure and the upper spacer portion. The second dielectric can include, for example, an oxide or a gas. The method may reduce effective capacitance and gate height loss, and improve gate-to-contact short margin.
    Type: Application
    Filed: March 21, 2019
    Publication date: September 24, 2020
    Inventors: Yanping Shen, Hui Zang, Jiehui Shu
  • Publication number: 20200303247
    Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to methods of forming a protective liner in transistor devices for protecting one or more gate spacers having a low-K dielectric material. The present disclosure further provides a semiconductor structure including a gate structure having a gate spacer, a trench having upper and lower sidewall portions adjacent to the gate spacer, the trench having a conductive structure over a device element and an adjoining insulative structure over an electrical isolation region, a dielectric liner disposed on the lower sidewall portion of the trench, and a protective liner disposed on the upper sidewall portion of the trench and within the insulative structure.
    Type: Application
    Filed: March 18, 2019
    Publication date: September 24, 2020
    Inventors: JIEHUI SHU, HUI ZANG, SCOTT HOWARD BEASOR, DALI SHAO
  • Patent number: 10784195
    Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Xiaoqiang Zhang, Haizhou Yin, Moosung M. Chae, Jinping Liu, Hui Zang
  • Patent number: 10784143
    Abstract: Structures that include a field effect-transistor and methods of forming a structure that includes a field-effect transistor. A semiconductor fin has an upper portion and a lower portion, and a trench isolation region surrounds the lower portion of the semiconductor fin. The trench isolation region has a top surface arranged above the lower portion of the semiconductor fin and arranged below the upper portion of the semiconductor fin. A dielectric layer arranged over the top surface of the trench isolation region. The dielectric layer is composed of a low-k dielectric material.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Guowei Xu, Hui Zang, Yue Zhong
  • Patent number: 10777642
    Abstract: One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a second straight sidewall spacer on the first straight sidewall spacer and forming a recessed layer of sacrificial material adjacent the second straight sidewall spacer such that the recessed layer of sacrificial material covers an outer surface of a first vertical portion of the second straight sidewall spacer while exposing a second vertical portion of the second straight sidewall spacer. In this example, the method may also include removing the second vertical portion of the second straight sidewall spacer, removing the recessed layer of sacrificial material and forming an epi material such that an edge of the epi material engages the outer surface of the first vertical portion of the second straight sidewall spacer.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Wei Hong, George R. Mulfinger, Hui Zang, Liu Jiang, Zhenyu Hu
  • Patent number: 10777637
    Abstract: One illustrative integrated circuit product disclosed herein includes a single diffusion break (SDB) isolation structure positioned between a first fin portion and a second fin portion, wherein the first fin portion comprises a first end surface and the second fin portion comprises a second end surface. In this example, the SDB structure includes a conformal liner layer that engages the first end surface of the first fin portion and the second end surface of the second fin portion, an insulating material positioned on the conformal liner layer, a cap structure positioned above an upper surface of the insulating material and an air gap positioned between a bottom surface of the cap structure and the upper surface of the insulating material.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hong Yu, Jiehui Shu, Hui Zang