Patents by Inventor Hui Zang

Hui Zang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method, apparatus, and system for improving scaling of isolation structures for gate, source, and/or drain contacts
    Patent number: 10707303
    Abstract: A semiconductor device, comprising a semiconductor substrate; an isolation layer disposed on the semiconductor substrate; a first active region and a second active region disposed at least partially above the isolation layer; a first gate structure and a second gate structure disposed on the isolation layer, the first active region, and the second active region; and an isolation pillar disposed on the isolation layer, between the first and second active regions, and between and in contact with the first and second gate structures, wherein the isolation pillar has an inverted-T shape. A method for making the semiconductor device. A system configured to implement the method and manufacture the semiconductor device.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Hui Zang, Zhenyu Owen Hu
  • Method, apparatus, and system for improved gate connections on isolation structures in FinFET devices
    Patent number: 10707207
    Abstract: A semiconductor device, comprising first and second sets of fins; first and second gate electrodes; first and second isolation structures each separating one of the gate electrodes into a first portion and a second portion; and first and second conductive structures wider than the corresponding isolation structure and disposed on an entirety of a top of the corresponding isolation structure and on a part of the top of each of the first and second portions of the corresponding gate electrode. A method for making the semiconductor device. A system configured to implement the method and manufacture the semiconductor device. The semiconductor device may have a low parasitic capacitance and high chip performance.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Dali Shao
  • Gate cut isolation formed as layer against sidewall of dummy gate mandrel
    Patent number: 10707206
    Abstract: A method of forming a gate cut isolation, a related structure and IC are disclosed. The method forms a dummy gate material mandrel having a sidewall positioned between and spaced from a first active region covered by the mandrel and a second active region not covered by the mandrel. A gate cut dielectric layer is formed against the sidewall of the mandrel, and may be trimmed. A dummy gate material may deposited to encase the remaining gate cut dielectric layer. Subsequent dummy gate formation and replacement metal gate processing forms a gate conductor with the gate cut isolation electrically isolating respective first and second portions of the gate conductor. The method creates a very thin, slightly non-vertical gate cut isolation, and eliminates the need to define a gate cut critical dimension or fill a small gate cut opening.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Laertis Economikos, Ruilong Xie
  • SEMICONDUCTOR STRUCTURE WITH SHAPED TRENCH AND METHODS OF FORMING THE SAME
    Publication number: 20200211903
    Abstract: The present disclosure generally relates to semiconductor device fabrication and integrated circuits. More particularly, the present disclosure relates to methods of forming a two-part trench in a semiconductor device that includes one or more field-effect transistors (FETs). The present method includes forming a semiconductor layer above a substrate, forming a mask layer above the semiconductor layer, forming a mask opening with sidewalls in the mask layer and exposing the semiconductor layer, depositing a profile control layer on the sidewalls of the mask opening, and forming a trench in the semiconductor layer by simultaneously etching the profile control layer and the exposed semiconductor layer, where the etching of the profile control layer forms the trench with top and bottom sections having different widths.
    Type: Application
    Filed: January 2, 2019
    Publication date: July 2, 2020
    Inventors: JIEHUI SHU, JESSICA MARY DECHENE, HUI ZANG, NAVED AHMED SIDDIQUI
  • Late gate cut using selective dielectric deposition
    Patent number: 10699957
    Abstract: Methods of forming a structure that includes field-effect transistor and structures that include a field effect-transistor. A dielectric cap is formed over a gate structure of a field-effect transistor, and an opening is patterned that extends fully through the dielectric cap to divide the dielectric cap into a first section and a second section spaced across the opening from the first surface. First and second dielectric spacers are respectively selectively deposited on respective first and second surfaces of the first and second sections of the dielectric cap to shorten the opening. A portion of the gate structure exposed through the opening between the first and second dielectric spacers is etched to form a cut that divides the gate electrode into first and second sections disconnected by the cut. A dielectric material is deposited in the opening and in the cut to form a dielectric pillar.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Jiehui Shu, Chanro Park, Laertis Economikos
  • Vertical-transport field-effect transistors having gate contacts located over the active region
    Patent number: 10699942
    Abstract: Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Chanro Park, Daniel Chanemougame, Steven Soss, Lars Liebmann, Hui Zang, Shesh Mani Pandey
  • GATE CONTACT STRUCTURES AND CROSS-COUPLED CONTACT STRUCTURES FOR TRANSISTOR DEVICES
    Publication number: 20200203497
    Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.
    Type: Application
    Filed: February 28, 2020
    Publication date: June 25, 2020
    Inventors: Ruilong Xie, Youngtag Woo, Daniel Chanemougame, Bipul C. Paul, Lars W. Liebmann, Heimanu Niebojewski, Xuelian Zhu, Lei Sun, Hui Zang
  • IC structure with air gap adjacent to gate structure and methods of forming same
    Patent number: 10692987
    Abstract: The disclosure provides an integrated circuit (IC) structure including a first spacer on a semiconductor fin adjacent a first portion of the gate structure, and having a first height above the semiconductor fin; a second spacer on the semiconductor fin adjacent the first spacer, such that the first spacer is horizontally between the first portion of the gate structure and a lower portion of the outer; and a gate cap positioned over the first portion of the gate structure and on the second spacer above the semiconductor fin. The gate cap defines an air gap horizontally between the first portion of the gate structure and an upper portion of the second spacer, and vertically between an upper surface of the first spacer and a lower surface of the gate cap.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: June 23, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Guowei Xu, Hui Zang
  • Interconnects with variable space mandrel cuts formed by block patterning
    Patent number: 10692812
    Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over an interlayer dielectric layer, and a block mask is formed that covers an area on the hardmask. A sacrificial layer is formed over the block mask and the hardmask, and the sacrificial layer is patterned to form a mandrel that extends across the block mask.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: June 23, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ravi Prakash Srivastava, Hui Zang, Jiehui Shu
  • SELF-ALIGNED CUTS IN AN INTERCONNECT STRUCTURE
    Publication number: 20200194306
    Abstract: Methods for forming a cut between interconnects and structures with cuts between interconnects. A layer is patterned to form first, second, and third features having a substantially parallel alignment with the second feature between the first feature and the third feature. A sacrificial layer is formed that is arranged between the first and second features and between the second and third features. The sacrificial layer is patterned to form a cut between the first and second features from which a portion of the sacrificial layer is fully removed and to form a cavity in a portion of the sacrificial layer between the second and third features. A dielectric layer is formed inside the cut between the first and second features. After depositing the section of the dielectric material and forming the dielectric layer, the sacrificial layer is removed.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 18, 2020
    Inventors: Ruilong Xie, Hui Zang, Lei Sun, Lars Liebmann, Daniel Chanemougame, Guillaume Bouche
  • Methods, apparatus, and manufacturing system for self-aligned patterning of contacts in a semiconductor device
    Patent number: 10685881
    Abstract: A method, apparatus, and manufacturing system are disclosed for a fin field effect transistor having a reduced risk of short circuits between a gate and a source/drain contact. In one embodiment, we disclose a semiconductor device including a fin structure comprising a fin body, source/drain regions, and a metal formation disposed above the source/drain regions, wherein the metal formation has a first height; and a gate structure between the source/drain regions, wherein each gate structure comprises spacers in contact with the metal formation, wherein the spacers have a second height less than the first height, a metal plug between the spacers and below the second height, and a T-shaped cap above the metal plug and having the first height.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: June 16, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Guowei Xu, Haiting Wang
  • Self-aligned cuts in an interconnect structure
    Patent number: 10685874
    Abstract: Methods for forming a cut between interconnects and structures with cuts between interconnects. A layer is patterned to form first, second, and third features having a substantially parallel alignment with the second feature between the first feature and the third feature. A sacrificial layer is formed that is arranged between the first and second features and between the second and third features. The sacrificial layer is patterned to form a cut between the first and second features from which a portion of the sacrificial layer is fully removed and to form a cavity in a portion of the sacrificial layer between the second and third features. A dielectric layer is formed inside the cut between the first and second features. After depositing the section of the dielectric material and forming the dielectric layer, the sacrificial layer is removed.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 16, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Hui Zang, Lei Sun, Lars Liebmann, Daniel Chanemougame, Guillaume Bouche
  • Gate structures
    Patent number: 10685840
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a plurality of gate structures comprising a gate cap, sidewall spacers and source and drain regions; source and drain metallization features extending to the source and drain regions; and a liner extending along an upper portion of the sidewall spacers of at least one of the plurality of gate structures.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: June 16, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Hui Zang
  • METHODS, APPARATUS AND SYSTEM FOR A SELF-ALIGNED GATE CUT ON A SEMICONDUCTOR DEVICE
    Publication number: 20200185509
    Abstract: At least one method, apparatus and system disclosed herein involves adjusting for a misalignment of a gate cut region with respect to semiconductor processing. A plurality of fins are formed on a semiconductor substrate. A gate region is formed over a portion of the fins. The gate region comprises a first dummy gate and a second dummy gate. A gate cut region is formed over the first dummy gate. A conformal fill material is deposited into the gate cut region. At least one subsequent processing step is performed.
    Type: Application
    Filed: December 30, 2019
    Publication date: June 11, 2020
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Laertis Economikos, Ruilong Xie
  • SINGLE DIFFUSION CUT FOR GATE STRUCTURES
    Publication number: 20200185266
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to single diffusion cut for gate structures and methods of manufacture. The structure includes a single diffusion break extending into a substrate between diffusion regions of adjacent gate structures, the single diffusion break filled with an insulator material and further comprising an undercut region lined with a liner material which is between the insulator material and the diffusion regions.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 11, 2020
    Inventors: Hui ZANG, Ruilong XIE, Jessica M. DECHENE
  • SINGLE DIFFUSION CUT FOR GATE STRUCTURES
    Publication number: 20200176444
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures composed of semiconductor material; a plurality of replacement gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of replacement gate structures; and a single diffusion break between the diffusion regions of the adjacent replacement gate structures, the single diffusion break being filled with an insulator material. In a first cross-sectional view, the single diffusion break extends into the semiconductor material and in a second cross-sectional view, the single diffusion break is devoid of semiconductor material of the plurality of fin structures.
    Type: Application
    Filed: November 29, 2018
    Publication date: June 4, 2020
    Inventors: Guowei XU, Hui ZANG, Ruilong XIE, Haiting WANG
  • MIDDLE OF LINE STRUCTURES
    Publication number: 20200176324
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures; source and drain regions adjacent to respective gate structures of the plurality of gate structures; metallization features contacting selected source and drain regions; and recessed metallization features contacting other selected source and drain regions.
    Type: Application
    Filed: November 29, 2018
    Publication date: June 4, 2020
    Inventors: Hui ZANG, Ruilong XIE
  • LATE GATE CUT USING SELECTIVE CONDUCTOR DEPOSITION
    Publication number: 20200176258
    Abstract: Methods of forming a structure that includes a field-effect transistor and structures that include a field effect-transistor. A cut is formed that extends through a gate structure of the field-effect transistor such that a gate electrode of the gate structure is divided into a first section having a first surface and a second section having a second surface spaced across the cut from the first surface. After forming the cut, a first section of a conductive layer is selectively deposited on the first surface of the first section of the gate electrode and a second section of the conductive layer is selectively deposited on the second surface of the second section of the gate electrode to shorten the cut. A dielectric material is deposited in the cut between the first and second sections of the conductive layer on the first and second surfaces of the gate electrode to form a dielectric pillar.
    Type: Application
    Filed: November 29, 2018
    Publication date: June 4, 2020
    Inventors: Hui Zang, David P. Brunco
  • NOVEL GATE STRUCTURE FOR A TRANSISTOR DEVICE WITH A NOVEL PILLAR STRUCTURE POSITIONED THEREABOVE
    Publication number: 20200176587
    Abstract: One illustrative transistor device disclosed herein includes a final gate structure that includes a gate insulation layer comprising a high-k material and a conductive gate, wherein the gate structure has an axial length in a direction that corresponds to a gate width direction of the transistor device. The device also includes a sidewall spacer contacting opposing lateral sidewalls of the final gate structure and a pillar structure (comprised of a pillar material) positioned above at least a portion of the final gate structure, wherein, when the pillar structure is viewed in a cross-section taken through the pillar structure in a direction that corresponds to the gate width direction of the transistor device, the pillar structure comprises an outer perimeter and wherein a layer of the high-k material is positioned around the entire outer perimeter of the pillar material.
    Type: Application
    Filed: January 30, 2020
    Publication date: June 4, 2020
    Inventors: Ruilong Xie, Youngtag Woo, Hui Zang
  • LATE GATE CUT USING SELECTIVE DIELECTRIC DEPOSITION
    Publication number: 20200168509
    Abstract: Methods of forming a structure that includes field-effect transistor and structures that include a field effect-transistor. A dielectric cap is formed over a gate structure of a field-effect transistor, and an opening is patterned that extends fully through the dielectric cap to divide the dielectric cap into a first section and a second section spaced across the opening from the first surface. First and second dielectric spacers are respectively selectively deposited on respective first and second surfaces of the first and second sections of the dielectric cap to shorten the opening. A portion of the gate structure exposed through the opening between the first and second dielectric spacers is etched to form a cut that divides the gate electrode into first and second sections disconnected by the cut. A dielectric material is deposited in the opening and in the cut to form a dielectric pillar.
    Type: Application
    Filed: November 27, 2018
    Publication date: May 28, 2020
    Inventors: Hui Zang, Ruilong Xie, Jiehui Shu, Chanro Park, Laertis Economikos