Abstract: A metallic stack and a preparing method therefor, and an electronic device including the metallic stack. The metallic stack includes at least one interconnection wire layer and at least one via layer alternately arranged on a substrate. At least one pair of interconnection wire layer and via layer in the metallic stack includes interconnection wires in the interconnection wire layer and conductive vias in the via layer, wherein the interconnection wire layer is closer to the substrate than the via layer. At least a part of the interconnection wires is integrated with the conductive vias on the at least a part of the interconnection wires.

Abstract: A metallization stack and a method of manufacturing the same, and an electronic device including the metallization stack are provided. The metallization stack may include at least one interconnection line layer and at least one via hole layer arranged alternately on a substrate. At least one pair of adjacent interconnection line layer and via hole layer in the metallization stack includes: an interconnection line in the interconnection line layer, and a via hole in the via hole layer. The interconnection line layer is closer to the substrate than the via hole layer. A peripheral sidewall of a via hole on at least part of the interconnection line does not exceed a peripheral sidewall of the at least part of the interconnection line.

Abstract: Disclosed are a semiconductor apparatus, a manufacturing method therefor, and an electronic equipment comprising the semiconductor apparatus. According to the embodiments, the semiconductor apparatus includes a first device and a second device on a substrate that are opposite each other. The first device and the second device each include a channel portion, source/drain portions on both sides of the channel portion that are connected to the channel portion, and a gate stack overlapping the channel portion. The channel portion includes a first portion extending in a vertical direction relative to the substrate and a second portion extending from the first portion in a transverse direction relative to the substrate. The second portion of the channel portion of the first device and the second portion of the channel portion of the second device extend toward or away from each other.

Abstract: The present disclosure provides a semiconductor device, a method for manufacturing the semiconductor device, and electronic equipment including the semiconductor device. According to embodiments, a semiconductor device may include a channel portion, source/drain portions in contact with the channel portion on opposite sides of the channel portion, and a gate stack intersecting the channel portion. The channel portion includes a first part extending in a vertical direction relative to the substrate and a second part extending from the first part in a lateral direction relative to the substrate.

Abstract: A semiconductor device with a U-shaped channel and a manufacturing method thereof and an electronic apparatus including the semiconductor device are disclosed. According to embodiments, the semiconductor device may include: a channel portion extending vertically on a substrate and having a U-shape in a plan view; source/drain portions located at upper and lower ends of the channel portion and along the U-shaped channel portion; and a gate stack overlapping the channel portion on an inner side of the U shape.

Abstract: A C-shaped active area semiconductor device and a method of manufacturing the same and electronic device including the semiconductor device are provided. According to embodiments, the semiconductor device includes: a channel portion extending vertically on a substrate; source/drain portions located at upper and lower ends of the channel portion relative to the substrate and along the channel portion, wherein the source/drain portion extends toward a side of the channel portion in a lateral direction relative to the substrate, so that the source/drain portions and the channel portion constitute a C-shaped structure; a gate stack that overlaps the channel portion on an inner sidewall of the C-shaped structure, wherein the gate stack has a portion surrounded by the C-shaped structure; and a back gate stack overlapping the channel portion on an outer sidewall of the C-shaped structure.

Abstract: A nanowire semiconductor device having a high-quality epitaxial layer and a method of manufacturing the same are provided. According to an embodiment, the semiconductor device may include: a substrate; one or more nanowires spaced apart from the substrate, wherein the nanowires each extend along a curved longitudinal extending direction; and one or more semiconductor layers formed around peripheries of the respective nanowires to at least partially surround the respective nanowires, wherein the respective semiconductor layers around the respective nanowires are spaced apart from each other.

Abstract: A semiconductor device and a method of manufacturing the same, and an electronic apparatus including the semiconductor device are provided. The semiconductor device includes: an active region, on a substrate, extending substantially in a vertical direction; a gate stack formed around at least a part of a periphery of the active region, the active region including a channel region opposite to the gate stack, and a first source/drain region and a second source/drain region, and the gate stack including a gate dielectric layer, a work function tuning layer and a gate electrode material layer, and the work function tuning layer being between the gate electrode material layer and the channel region; and a first low-k dielectric layer extending from a first end of the work function tuning layer to surround a first corner of an end portion, on a side facing the channel region, of the gate electrode material layer.

Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.

Abstract: Provided are a nanowire/nanosheet device with a support portion, a method of manufacturing the same, and an electronic apparatus including the nanowire/nanosheet device.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof, and an electronic device including the semiconductor device. The semiconductor device includes: a substrate; an active region including a first source/drain region, a channel region and a second source/drain region stacked sequentially on the substrate and adjacent to each other; a gate stack formed around an outer periphery of the channel region; and spacers formed around the outer periphery of the channel region, respectively between the gate stack and the first source/drain region and between the gate stack and the second source/drain region; wherein the spacers each have a thickness varying in a direction parallel to a top surface of the substrate.

Abstract: A semiconductor apparatus with an isolation portion between vertically adjacent elements and an electronic device including the semiconductor apparatus are provided. The semiconductor apparatus may include: a substrate; a first vertical semiconductor element and a second vertical semiconductor element stacked on the substrate sequentially, each of the first vertical semiconductor element and the second vertical semiconductor element including a first source/drain region, a channel region and a second source/drain region stacked sequentially in a vertical direction; and an isolation structure configured to electrically isolate the first vertical semiconductor element from the second vertical semiconductor element, and the isolation structure including a pn junction.

Abstract: Provided are a nanowire/nanosheet device with a support portion, a method of manufacturing the nanowire/nanosheet device, and an electronic apparatus including the nanowire/nanosheet device. According to the embodiments, the nanowire/nanosheet device may include: a substrate; a first source/drain layer and a second source/drain layer opposite to each other in a first direction on the substrate; a first nanowire/nanosheet spaced apart from a surface of the substrate and extending from the first source/drain layer to the second source/drain layer; one or more support portions penetrating the first nanowire/nanosheet in a direction perpendicular to the surface of the substrate; and a gate stack extending in a second direction to surround the first nanowire/nanosheet, wherein the second direction intersects the first direction.

Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the device. According to the embodiments, the semiconductor device may include: an active region extending substantially in a vertical direction on a substrate; a gate stack formed around at least a portion of an outer periphery of a middle section of the active region in the vertical direction, wherein the active region comprises a channel region opposite to the gate stack, and a first source/drain region and a second source/drain region located on two opposite sides of the channel region in the vertical direction; a first spacer located between a conductor layer of the gate stack and the first source/drain region, and a second spacer located between the conductor layer of the gate stack and the second source/drain region.

Abstract: A C-shaped active area semiconductor device and a method of manufacturing the same and electronic device including the semiconductor device are provided. According to embodiments, the semiconductor device includes: a channel portion extending vertically on a substrate; source/drain portions located at upper and lower ends of the channel portion relative to the substrate and along the channel portion, wherein the source/drain portion extends toward a side of the channel portion in a lateral direction relative to the substrate, so that the source/drain portions and the channel portion constitute a C-shaped structure; and a gate stack that overlaps the channel portion on an inner sidewall of the C-shaped structure, wherein the gate stack has a portion surrounded by the C-shaped structure.

Abstract: A Static Random Access Memory (SRAM) cell that may include a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor and a second pass-gate transistor provided at two levels on a substrate. The respective transistors may be vertical transistors. The first pull-up transistor and the second pull-up transistor may be provided at a first level, and the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor and the second pass-gate transistor may be provided at a second level different from the first level. A region where the first pull-up transistor and the second pull-up transistor are located and a region where the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor and the second pass-gate transistor are located may at least partially overlap in a vertical direction with respect to an upper surface of the substrate.

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same thereof, and an electronic apparatus including the semiconductor device. According to embodiments of the present disclosure, the semiconductor device includes a channel portion, source/drain portions connected to the channel portion on two opposite sides of the channel portion, and a gate stack intersecting with the channel portion. The channel portion includes a first portion extending in a vertical direction with respect to a substrate and a second portion extending from the first portion to two opposite sides in a lateral direction with respect to the substrate, respectively.

Abstract: The present disclosure relates to a travel pillow. The travel pillow comprises a connecting rod having a first end and a second end, and a first pillow body and a second pillow body. Each of the first pillow body and the second pillow body comprises a frame and a soft cushion mounted on the frame. One end of the frame of the first pillow body is coupled to the first end of the connecting rod. The first pillow body is configured to be rotated at the first end of the connecting rods and locked at a predetermined angle. One end of the frame of the second pillow body is coupled to the second end of the connecting rod. The second pillow body is configured to be rotated at the second end of the connecting rods and locked at a predetermined angle. The travel pillow has a height which is adjusted by changing the angle between the first pillow body and the connecting rod and the angle between the second pillow body and the connecting rod. Moreover, a fastening means is used for carrying and securing the travel pillow.

Abstract: An interconnection structure and a method of manufacturing the same, and an electronic device including the interconnection structure are provided.

Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.