Abstract: The present disclosure discloses a semiconductor device with C-shaped channel portion, a method of manufacturing the same, and an electronic apparatus including the same. According to the embodiments, the semiconductor device may comprise a channel portion on a substrate, the channel portion including two or more curved nanosheets or nanowires spaced apart from each other in a lateral direction relative to the substrate and each having a C-shaped cross section; source/drain portions respectively located at upper and lower ends of the channel portion relative to the substrate; and a gate stack surrounding an outer circumference of each nanosheet or nanowire in the channel portion.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET), a method for manufacturing MOSFET, and an electronic apparatus including MOSFET are disclosed. The MOSFET include: a vertical channel portion on a substrate; source/drain portions respectively located at upper and lower ends of the channel portion with respect to the substrate; and a gate stack opposite to the channel portion. The channel portion has doping concentration distribution, so that when the MOSFET is an n-type MOSFET (nMOSFET), a threshold voltage of a first portion of the channel portion close to one of the source/drain portions is lower than a threshold voltage of a second portion adjacent to the first portion; or when the MOSFET is a p-type MOSFET (pMOSFET), a threshold voltage of a first portion in the channel portion close to one of the source/drain portions is higher than a threshold voltage of a second portion adjacent to the first portion.

Abstract: The present disclosure provides a semiconductor device, a manufacturing method thereof, and an electronic device including the semiconductor device. According to an embodiment of the present disclosure, the semiconductor device may comprise: a substrate; a first device and a second device that are sequentially stacked on the substrate. Each of the first device and the second device comprises: a first source/drain layer, a channel layer, and a second source layer that are sequentially stacked from bottom to top, and a gate stack around at least a part of an outer periphery of the channel layer, wherein sidewalls of the respective channel layers of the first device and the second device extend at least partially along different crystal planes or crystal plane families.

Abstract: Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device. According to the embodiments, the semiconductor device may include: a nanosheet stack layer on a substrate including a plurality of nanosheets spaced apart from each other in a vertical direction relative to the substrate, wherein at least one of the plurality of nanosheets includes a first portion in a first orientation, and at least one of an upper surface and a lower surface of the first portion is not parallel to a horizontal surface of the substrate.

Abstract: A parallel structure comprising source/drain and channel layers alternately stacked on a substrate, and gate stacks formed around peripheries of the channel layers. Each of the channel layers, the source/drain layers on upper and lower sides of the channel layer, and the gate stack formed around the channel layer, form a semiconductor device. In each semiconductor device, one of the source/drain layers is in contact with a first electrically-conductive channel disposed on an outer periphery of the active region, the other is in contact with a second electrically-conductive channel on the outer periphery of the active region, and the gate stack is in contact with a third electrically-conductive channel disposed on the outer periphery of the active region. The first electrically-conductive channel is common to the semiconductor devices, the second electrically-conductive channel is common to the semiconductor devices, and the third electronically-conductive channel is common to the semiconductor devices.

Abstract: A method of manufacturing a semiconductor memory device is provided. The method include: providing a stack of a sacrificial layer, a first source/drain layer, a channel layer, and a second source/drain layer on a substrate; defining a plurality of pillar-shaped active regions arranged in rows and columns in the first source/drain layer, the channel layer, and the second source/drain layer; removing the sacrificial layer and forming a plurality of bit lines extending below the respective columns of active regions in a space left by the removal of the sacrificial layer; forming gate stacks around peripheries of the channel layer in the respective active regions; and forming a plurality of word lines between the respective rows of active regions, wherein each of the word lines is electrically connected to the gate stacks of the respective memory cells in a corresponding one of the rows.

Abstract: A semiconductor memory device that may include a substrate, an array of memory cells arranged in rows and columns, bit lines and word lines. The memory cells each may include a pillar-shaped active region extending vertically, which includes source/drain regions at upper and lower ends respectively and a channel region between the source/drain regions. The channel region may include a single-crystalline semiconductor material. The memory cells each may further include a gate stack formed around a periphery of the channel region. Each of the bit lines is located below a corresponding column, and electrically connected to the lower source/drain regions of the respective memory cells in the corresponding column. Each of the word lines is electrically connected to the gate stacks of the respective memory cells in a corresponding row.

Abstract: A semiconductor device with C-shaped channel portion and an electronic apparatus including the semiconductor device are disclosed. According to the embodiments, the semiconductor device may include a first semiconductor element and a second semiconductor element adjacent in a first direction. The first semiconductor element and the second semiconductor element may respectively include: a channel portion on a substrate, the channel portion including a curved nano-sheet or nano-wire with a C-shaped section; source/drain portions at upper and lower ends of the channel portion with respect to the substrate, respectively; and a gate stack surrounding a periphery of the channel portion. The channel portion of the first semiconductor element and the channel portion of the second semiconductor element may be substantially coplanar.

Abstract: A semiconductor apparatus including a capacitor and a method of manufacturing the same, and an electronic device including the semiconductor apparatus are provided. According to embodiments, the semiconductor apparatus may include: a vertical semiconductor device including an active region extending vertically on a substrate; and a capacitor including a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode sequentially stacked. The first capacitor electrode extends vertically on the substrate and includes a conductive material, and the conductive material includes at least one semiconductor element contained in the active region of the vertical semiconductor device.

Abstract: A semiconductor device and a manufacturing method thereof, and an electronic device including the semiconductor device. The semiconductor device includes: a substrate; an active region including a first source/drain region, a channel region and a second source/drain region stacked sequentially on the substrate and adjacent to each other; a gate stack formed around an outer periphery of the channel region; and spacers formed around the outer periphery of the channel region, respectively between the gate stack and the first source/drain region and between the gate stack and the second source/drain region; wherein the spacers each have a thickness varying in a direction perpendicular to a direction from the first source/drain region pointing to the second source/drain region; wherein the spacers each have the thickness gradually decreasing from a surface exposed on an outer peripheral surface of the active region to an inside of the active region.

Abstract: A semiconductor device with a C-shaped channel portion, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device are provided. The semiconductor device may include: a channel portion on a substrate, wherein the channel portion includes a curved nanosheet/nanowire with a C-shaped cross section; source/drain portions respectively located at upper and lower ends of the channel portion with respect to the substrate; and a gate stack surrounding a periphery of the channel portion.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof, and an electronic device including the semiconductor device. The method includes: forming a first material layer and a second material layer sequentially on a substrate; defining an active region of the semiconductor device on the substrate, the first material layer and the second material layer, wherein the active region includes a channel region; forming spacers around an outer periphery of the channel region, respectively at set positions of the substrate and the second material layer; forming a first source/drain region and a second source/drain region on the substrate and the second material layer respectively; and forming a gate stack around the outer periphery of the channel region; wherein the spacers each have a thickness varying in a direction perpendicular to a direction from the first source/drain region pointing to the second source/drain region.

Abstract: A multi-gate FinFET including a negative capacitor connected to one of its gates, a method of manufacturing the same, and an electronic device comprising the same are disclosed. In one aspect, the FinFET includes a fin extending in a first direction on a substrate, a first gate extending in a second direction crossing the first direction on the substrate on a first side of the fin to intersect the fin, a second gate opposite to the first gate and extending in the second direction on the substrate on a second side of the fin opposite to the first side to intersect the fin, a metallization stack provided on the substrate and above the fin and the first and second gates, and a negative capacitor formed in the metallization stack and connected to the second gate.

Abstract: A metallization stack and a method of manufacturing the same, and an electronic device including the metallization stack are provided. The metallization stack may include at least one interconnection line layer and at least one via hole layer arranged alternately on a substrate. At least one pair of adjacent interconnection line layer and via hole layer in the metallization stack includes: an interconnection line in the interconnection line layer, and a via hole in the via hole layer. The interconnection line layer is closer to the substrate than the via hole layer. A peripheral sidewall of a via hole on at least part of the interconnection line does not exceed a peripheral sidewall of the at least part of the interconnection line.

Abstract: A metallic stack and a preparing method therefor, and an electronic device including the metallic stack. The metallic stack includes at least one interconnection wire layer and at least one via layer alternately arranged on a substrate. At least one pair of interconnection wire layer and via layer in the metallic stack includes interconnection wires in the interconnection wire layer and conductive vias in the via layer, wherein the interconnection wire layer is closer to the substrate than the via layer. At least a part of the interconnection wires is integrated with the conductive vias on the at least a part of the interconnection wires.

Abstract: Disclosed are a semiconductor apparatus, a manufacturing method therefor, and an electronic equipment comprising the semiconductor apparatus. According to the embodiments, the semiconductor apparatus includes a first device and a second device on a substrate that are opposite each other. The first device and the second device each include a channel portion, source/drain portions on both sides of the channel portion that are connected to the channel portion, and a gate stack overlapping the channel portion. The channel portion includes a first portion extending in a vertical direction relative to the substrate and a second portion extending from the first portion in a transverse direction relative to the substrate. The second portion of the channel portion of the first device and the second portion of the channel portion of the second device extend toward or away from each other.

Abstract: The present disclosure provides a semiconductor device, a method for manufacturing the semiconductor device, and electronic equipment including the semiconductor device. According to embodiments, a semiconductor device may include a channel portion, source/drain portions in contact with the channel portion on opposite sides of the channel portion, and a gate stack intersecting the channel portion. The channel portion includes a first part extending in a vertical direction relative to the substrate and a second part extending from the first part in a lateral direction relative to the substrate.

Abstract: A C-shaped active area semiconductor device and a method of manufacturing the same and electronic device including the semiconductor device are provided. According to embodiments, the semiconductor device includes: a channel portion extending vertically on a substrate; source/drain portions located at upper and lower ends of the channel portion relative to the substrate and along the channel portion, wherein the source/drain portion extends toward a side of the channel portion in a lateral direction relative to the substrate, so that the source/drain portions and the channel portion constitute a C-shaped structure; a gate stack that overlaps the channel portion on an inner sidewall of the C-shaped structure, wherein the gate stack has a portion surrounded by the C-shaped structure; and a back gate stack overlapping the channel portion on an outer sidewall of the C-shaped structure.

Abstract: A semiconductor device with a U-shaped channel and a manufacturing method thereof and an electronic apparatus including the semiconductor device are disclosed. According to embodiments, the semiconductor device may include: a channel portion extending vertically on a substrate and having a U-shape in a plan view; source/drain portions located at upper and lower ends of the channel portion and along the U-shaped channel portion; and a gate stack overlapping the channel portion on an inner side of the U shape.

Abstract: A nanowire semiconductor device having a high-quality epitaxial layer and a method of manufacturing the same are provided. According to an embodiment, the semiconductor device may include: a substrate; one or more nanowires spaced apart from the substrate, wherein the nanowires each extend along a curved longitudinal extending direction; and one or more semiconductor layers formed around peripheries of the respective nanowires to at least partially surround the respective nanowires, wherein the respective semiconductor layers around the respective nanowires are spaced apart from each other.