Patents by Inventor Hung-Che Liao

Hung-Che Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11121141
    Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Hsin-Chi Chen
  • Publication number: 20210210381
    Abstract: A method of making a semiconductor structure includes depositing a first passivation material between adjacent conductive elements on a substrate, wherein a bottommost surface of the first passivation material is coplanar with a bottommost surface of each of the adjacent conductive elements. The method further includes depositing a second passivation material on the substrate, wherein the second passivation material contacts a sidewall of each of the adjacent conductive elements and a sidewall of the first passivation material, a bottommost surface of the second passivation material is coplanar with the bottommost surface of each of the adjacent conductive elements, and the second passivation material is different from the first passivation material.
    Type: Application
    Filed: March 19, 2021
    Publication date: July 8, 2021
    Inventors: Chih-Ming LEE, Hung-Che LIAO, Kun-Tsang CHUANG, Wei-Chung LU
  • Patent number: 10964589
    Abstract: A semiconductor structure includes a substrate, first and second conductors, a passivation material, and a passivation sidewall block. The first and second conductors are on the substrate. The passivation material is between the first and second conductors. The passivation sidewall block is on sidewalls of the first and second conductors and the passivation material.
    Type: Grant
    Filed: August 13, 2017
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chih-Ming Lee, Hung-Che Liao, Kun-Tsang Chuang, Wei-Chung Lu
  • Publication number: 20200152648
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
  • Patent number: 10535670
    Abstract: A method of manufacturing a non-volatile memory is described. A substrate including a first region and a second region located at periphery of the first region is provided. A plurality of stacked structures are formed on the first region of the substrate. A wall structure is formed on the second region of the substrate. A conductive layer is formed over the substrate. A bottom anti-reflective coating is formed over the conductive layer. The bottom anti-reflective coating and the conductive layer are etched back. The conductive layer is patterned.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
  • Publication number: 20190259771
    Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.
    Type: Application
    Filed: May 6, 2019
    Publication date: August 22, 2019
    Inventors: Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Hsin-Chi Chen
  • Patent number: 10283510
    Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Hsin-Chi Chen
  • Patent number: 10283604
    Abstract: A method of fabricating semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. A first inter layer dielectric layer is deposited on the gate structures. A first contact plug is formed in the first inter layer dielectric layer in between every two immediately adjacent gate structures. An etch stop layer is deposited on the first inter layer dielectric layer. A second inter layer dielectric layer is deposited on the first inter layer dielectric layer. A second contact plug is formed in the second inter layer dielectric layer aligning with the first contact plug. A metal layer is deposited overlying the second inter layer dielectric layer and the second contact plug.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Szu-Hsien Lu, Hung-Che Liao, Kun-Tsang Chuang, Shih-Lu Hsu, Yu-Chu Lin, Jyun-Guan Jhou
  • Publication number: 20180006046
    Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.
    Type: Application
    Filed: September 18, 2017
    Publication date: January 4, 2018
    Inventors: Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Hsin-Chi Chen
  • Publication number: 20170358485
    Abstract: A semiconductor structure includes a substrate, first and second conductors, a passivation material, and a passivation sidewall block. The first and second conductors are on the substrate. The passivation material is between the first and second conductors. The passivation sidewall block is on sidewalls of the first and second conductors and the passivation material.
    Type: Application
    Filed: August 13, 2017
    Publication date: December 14, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Ming LEE, Hung-Che LIAO, Kun-Tsang CHUANG, Wei-Chung LU
  • Patent number: 9825046
    Abstract: A flash memory cell structure includes a semiconductor substrate, a pad dielectric layer, a floating gate, a control gate, and a blocking layer. The pad dielectric layer is disposed on the semiconductor substrate. The floating gate is disposed over the pad dielectric layer, in which the floating gate has a top surface opposite to the pad dielectric layer, and the top surface includes at least one recess formed thereon. The control gate is disposed over the top surface of the floating gate. The blocking layer is disposed between the floating gate and the control gate.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chu Lin, Hung-Che Liao, Kun-Tsang Chuang, Shih-Lu Hsu
  • Patent number: 9768182
    Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Hsin-Chi Chen
  • Publication number: 20170250188
    Abstract: A method of manufacturing a non-volatile memory is described. A substrate including a first region and a second region located at periphery of the first region is provided. A plurality of stacked structures are formed on the first region of the substrate. A wall structure is formed on the second region of the substrate. A conductive layer is formed over the substrate. A bottom anti-reflective coating is formed over the conductive layer. The bottom anti-reflective coating and the conductive layer are etched back. The conductive layer is patterned.
    Type: Application
    Filed: February 25, 2016
    Publication date: August 31, 2017
    Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
  • Patent number: 9735049
    Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes receiving a substrate with two sections of conductors thereon that are adjacent to each other, and a valley between the two sections of the conductors, filling the valley with a first passivation material to form a passivation valley, applying a second passivation material overlying the two sections of conductors and the passivation valley and over the substrate, and removing the second passivation material overlying the two sections of conductors and the passivation valley, and the second passivation material over the substrate but not in contact with the two sections of conductors and the passivation valley.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: August 15, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Ming Lee, Hung-Che Liao, Kun-Tsang Chuang, Wei-Chung Lu
  • Publication number: 20170194336
    Abstract: A flash memory cell structure includes a semiconductor substrate, a pad dielectric layer, a floating gate, a control gate, and a blocking layer. The pad dielectric layer is disposed on the semiconductor substrate. The floating gate is disposed over the pad dielectric layer, in which the floating gate has a top surface opposite to the pad dielectric layer, and the top surface includes at least one recess formed thereon. The control gate is disposed over the top surface of the floating gate. The blocking layer is disposed between the floating gate and the control gate.
    Type: Application
    Filed: January 5, 2016
    Publication date: July 6, 2017
    Inventors: Yu-Chu LIN, Hung-Che LIAO, Kun-Tsang CHUANG, Shih-Lu HSU
  • Patent number: 9666588
    Abstract: A non-volatile memory cell formed using damascene techniques includes a floating gate electrode that includes a recess lined with a control gate dielectric and filled with the control gate electrode material. The control gate material is a composite ONO, oxide-nitride-oxide sandwich dielectric in one embodiment. The floating gate transistors of the non-volatile memory cell include a high gate coupling ratio due to the increased area between the floating gate electrode and the control gate electrode.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Yu Chiu, Hung-Che Liao
  • Publication number: 20170148667
    Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes receiving a substrate with two sections of conductors thereon that are adjacent to each other, and a valley between the two sections of the conductors, filling the valley with a first passivation material to form a passivation valley, applying a second passivation material overlying the two sections of conductors and the passivation valley and over the substrate, and removing the second passivation material overlying the two sections of conductors and the passivation valley, and the second passivation material over the substrate but not in contact with the two sections of conductors and the passivation valley.
    Type: Application
    Filed: November 25, 2015
    Publication date: May 25, 2017
    Inventors: Chih-Ming LEE, Hung-Che LIAO, Kun-Tsang CHUANG, Wei-Chung LU
  • Publication number: 20170110466
    Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.
    Type: Application
    Filed: May 18, 2016
    Publication date: April 20, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chiang-Ming CHUANG, Chien-Hsuan LIU, Chih-Ming LEE, Kun-Tsang CHUANG, Hung-Che LIAO, Hsin-Chi CHEN
  • Publication number: 20170033047
    Abstract: A method of fabricating semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. A fist inter layer dielectric layer is deposited on the gate structures. A first contact plug is formed in the first inter layer dielectric layer in between every two immediately adjacent gate structures. An etch stop layer is deposited on the first inter layer dielectric layer. A second inter layer dielectric layer is deposited on the first inter layer dielectric layer. A second contact plug is formed in the second inter layer dielectric layer aligning with the first contact plug. A metal layer is deposited overlying the second inter layer dielectric layer and the second contact plug.
    Type: Application
    Filed: July 31, 2015
    Publication date: February 2, 2017
    Inventors: Szu-Hsien LU, Hung-Che LIAO, Kun-Tsang CHUANG, Shih-Lu HSU, Yu-Chu LIN, Jyun-Guan JHOU
  • Patent number: 9449976
    Abstract: A novel semiconductor device structure includes a first-conductivity-type semiconductor substrate, an isolated region, a first-conductivity-type MOS region, and a second-conductivity-type MOS region. A first-conductivity-type MOS transistor locates in the first-conductivity-type MOS region with a second-conductivity-type well surrounding, and a first-conductivity-type deep well surrounding the second-conductivity-type well with a second-conductivity-type deep well surrounding. In the second-conductivity-type MOS region, a second-conductivity-type MOS transistor is formed with a first-conductivity-type well surrounding. The first-conductivity-type deep well and the second-conductivity-type deep well are sufficiently reducing the noise and current leakage from other devices or from the semiconductor substrate.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: September 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Ching Wu, Hsiang-Hui Tsai, Po-Jen Wang, Hung-Che Liao