Patents by Inventor Hung-Hsin Hsu
Hung-Hsin Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120325Abstract: A stacked package structure and a manufacturing method thereof are provided. The stacked package structure includes an upper redistribution layer, a first chip, and an upper molding layer. The first chip is disposed on the upper redistribution layer and is electrically connected to the upper redistribution layer. The upper molding layer is disposed on the first chip and the upper redistribution layer, and is configured to package the first chip. The upper molding layer includes a recess, the recess is recessed relative to a surface of the upper molding layer away from the upper redistribution layer, and the recess is circumferentially formed around a periphery of the upper molding layer.Type: ApplicationFiled: May 31, 2023Publication date: April 11, 2024Applicant: POWERTECH TECHNOLOGY INC.Inventors: Pei-chun TSAI, Hung-hsin HSU, Shang-yu CHANG CHIEN, Chia-ling LEE
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Patent number: 11916035Abstract: A packaging structure including first, second, and third dies, an encapsulant, a circuit structure, and a filler is provided. The encapsulant covers the first die. The circuit structure is disposed on the encapsulant. The second die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die has an optical signal transmission area. The filler is disposed between the second die and the circuit structure and between the third die and the circuit structure. A groove is present on an upper surface of the circuit structure. The upper surface includes first and second areas located on opposite sides of the groove. The filler directly contacts the first area. The filler is away from the second area. A manufacturing method of a packaging structure is also provided.Type: GrantFiled: August 3, 2021Date of Patent: February 27, 2024Assignee: Powertech Technology Inc.Inventors: Shang-Yu Chang Chien, Nan-Chun Lin, Hung-Hsin Hsu
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Patent number: 11911782Abstract: A nozzle flow stirring pipe includes a pipe body and a nozzle. The pipe body is cylindrical and includes an inner pipe member and an outer pipe member. The inner pipe member has a liquid-extracting channel. The outer pipe member fits around the inner pipe member. A reflow channel is defined between an inner wall of the outer pipe member and an outer wall of the inner pipe member. The nozzle is disposed at one end of the pipe body. The inner pipe member is penetratingly disposed at the nozzle and exposed from below. The nozzle has a plurality of liquid-ejecting pores in communication with one end of the reflow channel.Type: GrantFiled: September 15, 2021Date of Patent: February 27, 2024Assignee: ASIA IC MIC-PROCESS, INC.Inventors: Hung-Hsin Hsu, Yan-Lan Chiou
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Patent number: 11769763Abstract: A package structure including a first die, an encapsulant, a first circuit structure, a second circuit structure, a conductive connector, a second die, and a filler is provided. The encapsulant covers the first die and has a first surface and a second surface opposite to each other. The first circuit structure is disposed on the first surface. The second circuit structure is disposed on the second surface. The conductive connector penetrates the encapsulant. The second die is disposed on the second circuit structure. The second die has an optical signal transmission area. The filler is disposed between the second die and the second circuit structure. An upper surface of the second circuit structure has a groove. The upper surface includes a first area and a second area disposed on opposite sides of the groove. The filler directly contacts the first area. The filler is disposed away from the second area.Type: GrantFiled: July 26, 2021Date of Patent: September 26, 2023Assignee: Powertech Technology Inc.Inventors: Shang-Yu Chang Chien, Nan-Chun Lin, Hung-Hsin Hsu
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Publication number: 20230290730Abstract: A package device and a manufacturing method thereof are provided. The package device includes a substrate, a plurality of conductive pillars, at least one bridge chip, a photosensitive encapsulation layer, a redistribution layer, and at least two active chips. The conductive pillars and the bridge chip are disposed on the substrate. The photosensitive encapsulation layer surrounds the bridge chip and the conductive pillars, in which a distance between a top surface of the bridge chip and a top surface of the photosensitive encapsulation layer is less than a distance between a top surface of one of the conductive pillars and the top surface of the photosensitive encapsulation layer. The redistribution layer is disposed on the photosensitive encapsulation layer, the active chips are disposed on the redistribution layer, and the bridge chip is coupled between the active chips.Type: ApplicationFiled: December 8, 2022Publication date: September 14, 2023Applicant: POWERTECH TECHNOLOGY INC.Inventors: Shang-Yu Chang Chien, Nan-Chun Lin, Hung-Hsin Hsu
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Publication number: 20230282587Abstract: A package device and a manufacturing method thereof are provided. The package device includes a substrate, a plurality of conductive pillars, a redistribution layer, at least one bridge chip, at least two active chips, an encapsulant, and an underfill layer. The conductive pillars are disposed on the substrate side by side, the redistribution layer is disposed on the conductive pillars, and the bridge chip is disposed between the substrate and the redistribution layer. The active chips are disposed on the redistribution layer, the bridge chip is coupled between the active chips, and the encapsulant is disposed on the redistribution layer and surrounds the active chips. The underfill layer is disposed between adjacent two of the conductive pillars and between one of the conductive pillars and the bridge chip.Type: ApplicationFiled: November 28, 2022Publication date: September 7, 2023Applicant: POWERTECH TECHNOLOGY INC.Inventors: Shang-Yu Chang Chien, Nan-Chun Lin, Hung-Hsin Hsu
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Publication number: 20230197647Abstract: Provided is an integrated antenna package structure including a chip, a circuit structure, a shielding body, an encapsulant, a first antenna layer, a dielectric body, and a second antenna layer. The circuit structure is electrically connected to the chip. The shielding body is disposed on the circuit structure and has an accommodating space. The chip is disposed in the accommodating space of the shielding body. The encapsulant is disposed on the circuit structure and covers the chip. The first antenna layer is disposed on the circuit structure and is electrically connected to the circuit structure. The dielectric body is disposed on the encapsulant. The second antenna layer is disposed on the dielectric body. A manufacturing method of the integrated antenna package structure is also provided.Type: ApplicationFiled: November 30, 2022Publication date: June 22, 2023Applicant: Powertech Technology Inc.Inventors: Shang-Yu Chang Chien, Nan-Chun Lin, Hung-Hsin Hsu
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Patent number: 11670611Abstract: A semiconductor package comprising plurality of bumps and fabricating method thereof. The package has a chip, a plurality of first and second bumps, an encapsulation, a redistribution. The chip has a plurality of pads and an active area and the active surface has a first area and a second area surrounding the first, the pads formed on a first area of the active surface, each first bump formed on the corresponding pad. The second bumps are formed on the second area, each second bump has first and second different width layers. The encapsulation encapsulates the chip and bumps and is ground to expose the bumps therefrom. During grinding, all of the first bumps are completely exposed by determining a width of an exposed surface of the second bump to electrically connect to the redistribution is increased. Therefore, a shallow-grinding or over-grinding does not occur.Type: GrantFiled: August 3, 2021Date of Patent: June 6, 2023Assignee: Powertech Technology Inc.Inventors: Shang-Yu Chang-Chien, Hung-Hsin Hsu, Nan-Chun Lin
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Patent number: 11637071Abstract: A package structure, including a conductive element, multiple dies, a dielectric body, a circuit layer and a patterned insulating layer, is provided. The multiple dies are disposed on the conductive element. A portion of the conductive element surrounds the multiple dies. The dielectric body covers the multiple dies. The circuit layer is disposed on the dielectric body. The circuit layer is electrically connected to the multiple dies. The patterned insulating layer covers the circuit layer. A portion of the patterned insulating layer is disposed between the dies that are adjacent. A manufacturing method of a package structure is also provided.Type: GrantFiled: January 27, 2021Date of Patent: April 25, 2023Assignee: Powertech Technology Inc.Inventors: Shang-Yu Chang Chien, Nan-Chun Lin, Hung-Hsin Hsu
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Publication number: 20230110079Abstract: A fan-out package structure and a manufacturing method thereof are provided. The fan-out package structure includes an upper redistribution layer, a die, a passive element, and an active element. The upper redistribution layer includes a first surface and a second surface opposite to the first surface. The die is disposed on the first surface of the upper redistribution layer and is electrically connected to the upper redistribution layer. The passive element is disposed on the second surface of the upper redistribution layer and is electrically connected to the upper redistribution layer. The active element is disposed on the second surface of the upper redistribution layer and is electrically connected to the upper redistribution layer. The active element is laterally adjacent to the passive element, and the die is electrically connected to the active element and the passive element through the upper redistribution layer.Type: ApplicationFiled: August 20, 2022Publication date: April 13, 2023Applicant: POWERTECH TECHNOLOGY INC.Inventors: Pei-chun Tsai, Hung-hsin Hsu, Ching-wei Liao, Shang-yu Chang Chien
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Patent number: 11617993Abstract: A material mixing and supplying system is provided. The material mixing and supplying system includes a feeding module, at least three mixing and supplying barrels, a supply module, and a control unit, wherein the three mixing and supplying barrels are capable of mixing and supplying the mixed material. The supplying time of the mixed material is greater than a sum of the feeding time and the mixing time. A total operation number of the at least three mixing and supplying barrels is determined by a set amount of mixed material to be supplied by the material mixing and supplying system, and a total time to finish supplying the set amount of mixed material is determined by the total operation number.Type: GrantFiled: February 18, 2020Date of Patent: April 4, 2023Assignee: ASIA IC MIC-PROCESS, INC.Inventors: Hung-Hsin Hsu, Yan-Lan Chiou
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Patent number: 11569210Abstract: A package structure, including a redistribution circuit layer, a first die, a dielectric body, a first connection circuit, a patterned insulating layer, a second die and a third die, is provided. The first die is disposed on the redistribution circuit layer and is electrically connected to the redistribution circuit layer. The dielectric body is disposed on the redistribution circuit layer and covers the first die. The first connection circuit is disposed on the dielectric body and is electrically connected to the redistribution circuit layer. The patterned insulating layer covers the first connection circuit. A portion of the patterned insulating layer is embedded in the dielectric body. The second die is disposed on the dielectric body and is electrically connected to the first connection circuit. The third die is disposed on the redistribution circuit layer, is opposite to the first die, and is electrically connected to the redistribution circuit layer.Type: GrantFiled: June 9, 2021Date of Patent: January 31, 2023Assignee: Powertech Technology Inc.Inventors: Shang-Yu Chang Chien, Nan-Chun Lin, Hung-Hsin Hsu
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Patent number: 11557533Abstract: A package structure including a redistribution circuit structure, a first chip, a second chip, a first circuit board, a second circuit board, and a plurality of conductive terminals is provided. The redistribution circuit structure has a first connection surface and a second connection surface opposite to the first connection surface. The first chip and the second chip are disposed on the first connection surface and are electrically connected to the redistribution circuit structure. The first circuit board and the second circuit board are disposed on the second connection surface and are electrically connected to the redistribution circuit structure. The conductive terminals are disposed on the first circuit board or the second circuit board. The conductive terminals are electrically connected to the first circuit board or the second circuit board. A manufacturing method of a package structure is also provided.Type: GrantFiled: October 27, 2020Date of Patent: January 17, 2023Assignee: Powertech Technology Inc.Inventors: Hung-Hsin Hsu, Nan-Chun Lin
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Patent number: 11545423Abstract: The disclosure provides a package structure including a redistribution circuit structure, a first circuit board, a second circuit board, a first insulator, multiple conductive terminals, and a package. The redistribution circuit structure has a first connection surface and a second connection surface opposite to each other. The first circuit board and the second circuit board are disposed on the first connection surface and are connected electrically to the redistribution circuit structure. The first insulator is disposed on the first connection surface and covers the first circuit board and the second circuit board. The conductive terminals are connected electrically to and disposed on the first circuit board or the second circuit board. The package is disposed on the second connection surface and is connected electrically to the redistribution circuit structure. A manufacturing method of a package structure is also provided.Type: GrantFiled: November 18, 2020Date of Patent: January 3, 2023Assignee: Powertech Technology Inc.Inventors: Shang-Yu Chang Chien, Nan-Chun Lin, Hung-Hsin Hsu
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Patent number: 11545424Abstract: A package structure including a redistribution circuit structure, an insulator, a plurality of conductive connection pieces, a first chip, a second chip, an encapsulant, a third chip, and a plurality of conductive terminals is provided. The redistribution circuit structure has first and second connection surfaces opposite to each other. The insulator is embedded in and penetrates the redistribution circuit structure. The conductive connection pieces penetrate the insulator. The first and second chips are disposed on the first connection surface. The encapsulant is disposed on the redistribution circuit structure and at least laterally covers the first and second chips. The third chip is disposed on the second connection surface and electrically connected to the first and second chips through the conductive connection pieces. The conductive terminals are disposed on the second connection surface and electrically connected to the first chip or the second chip through the redistribution circuit structure.Type: GrantFiled: November 19, 2020Date of Patent: January 3, 2023Assignee: Powertech Technology Inc.Inventors: Shang-Yu Chang Chien, Nan-Chun Lin, Hung-Hsin Hsu
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Patent number: 11532575Abstract: An integrated antenna package structure including a chip, a circuit layer, an encapsulant, a coupling end, an insulating layer, a conductive connector, a dielectric substrate, and an antenna is provided. The circuit layer is electrically connected to the chip. The encapsulant is disposed on the circuit layer and covers the chip. The coupling end is disposed on the encapsulant. The insulating layer covers the coupling end. The insulating layer is not externally exposed. The conductive connector penetrates the encapsulant. The coupling end is electrically connected to the circuit layer by the conductive connection. The dielectric substrate is disposed on the encapsulant and covers the coupling end. The antenna is disposed on the dielectric substrate. A manufacturing method of an integrated antenna package structure is also provided.Type: GrantFiled: September 6, 2019Date of Patent: December 20, 2022Assignee: Powertech Technology Inc.Inventors: Han-Wen Lin, Hung-Hsin Hsu, Shang-Yu Chang Chien, Nan-Chun Lin
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Patent number: 11518662Abstract: A lid opening component, a lid opening device, and a suction system are disclosed. The suction system includes the lid opening device and a suction assembly, wherein the lid opening device includes a positioning assembly and a lid opening assembly having the lid opening components, and the lid opening component includes a needle holder, a plurality of unpowered needles, and a drive part. The suction system identifies the locations of a container and its lids through the positioning assembly of the lid opening device, opens the container's lids by fitting the unpowered needles of the lid opening components in with the surfaces of the container's lids and rotating the lid opening components of the lid opening assembly, and by moving the suction assembly to the openings of the container, draws out the content in the container through the suction assembly.Type: GrantFiled: April 29, 2020Date of Patent: December 6, 2022Assignee: ASIA IC MIC-PROCESS, INC.Inventors: Hung-Hsin Hsu, Yan-Lan Chiou
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Patent number: 11522000Abstract: A semiconductor package structure including a sensor die, a substrate, a light blocking layer, a circuit layer, a dam structure and an underfill is provided. The sensor die has a sensing surface. The sensing surface includes an image sensing area and a plurality of conductive bumps. The substrate is disposed on the sensing surface. The light blocking layer is located between the substrate and the sensor die. The circuit layer is disposed on the light blocking layer. The sensor die is electrically connected to the circuit layer by the conductive bumps. The dam structure is disposed on the substrate and surrounds the image sensing area. Opposite ends of the dam structure directly contact the sensor die and the light blocking layer. The underfill is disposed between the dam structure and the conductive bumps.Type: GrantFiled: April 22, 2020Date of Patent: December 6, 2022Assignee: Powertech Technology Inc.Inventors: Hung-Hsin Hsu, Wen-Hsiung Chang
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Publication number: 20220328422Abstract: A fan-out semiconductor package includes: a redistribution structure; a functional chip coupled to the redistribution structure; an isolation structure disposed on the redistribution structure and including a body formed with through-holes; a shielding structure disposed on the isolation structure and the redistribution structure; a first conductive pattern structure disposed on the isolation structure and extending through the through-holes of the isolation structure; an encapsulating structure disposed on the isolation structure, the shielding structure and the first conductive pattern structure; and a second conductive pattern structure disposed on the encapsulating structure. A method for manufacturing the fan-out semiconductor package is also disclosed.Type: ApplicationFiled: November 12, 2021Publication date: October 13, 2022Applicant: Powertech Technology Inc.Inventors: Shang-Yu CHANG CHIEN, Nan-Chun LIN, Hung-Hsin HSU
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Publication number: 20220320052Abstract: A package structure, including a redistribution circuit layer, a first die, a dielectric body, a first connection circuit, a patterned insulating layer, a second die and a third die, is provided. The first die is disposed on the redistribution circuit layer and is electrically connected to the redistribution circuit layer. The dielaectric body is disposed on the redistribution circuit layer and covers the first die. The first connection circuit is disposed on the dielectric body and is electrically connected to the redistribution circuit layer. The patterned insulating layer covers the first connection circuit. A portion of the patterned insulating layer is embedded in the dielectric body. The second die is disposed on the dielectric body and is electrically connected to the first connection circuit. The third die is disposed on the redistribution circuit layer, is opposite to the first die, and is electrically connected to the redistribution circuit layer.Type: ApplicationFiled: June 9, 2021Publication date: October 6, 2022Applicant: Powertech Technology Inc.Inventors: Shang-Yu Chang Chien, Nan-Chun Lin, Hung-Hsin Hsu