Patents by Inventor Hung-Hua Lin

Hung-Hua Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9242853
    Abstract: The present disclosure relates to a method of gettering that provides for a high efficiency gettering process by depositing a gettering material on a roughened substrate surface, and an associated apparatus. In some embodiments, the method is performed by providing a substrate into a processing chamber having residual gases. One or more cavities are formed in the substrate at locations between bonding areas on a top surface of the substrate. Respective cavities have roughened interior surfaces that vary in a plurality of directions. A getter layer is deposited into the one or more cavities. The roughened interior surfaces of the one or more cavities enable the substrate to more effectively absorb the residual gases, thereby increasing the efficiency of the gettering process.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan-Chih Hsieh, Li-Cheng Chu, Hung-Hua Lin, Chih-Jen Chan, Lan-Lin Chao
  • Patent number: 9181083
    Abstract: A device includes a substrate, a routing conductive line over the substrate, a dielectric layer over the routing conductive line, and an etch stop layer over the dielectric layer. A Micro-Electro-Mechanical System (MEMS) device has a portion over the etch stop layer. A contact plug penetrates through the etch stop layer and the dielectric layer. The contact plug connects the portion of the MEMS device to the routing conductive line. An escort ring is disposed over the etch stop layer and under the MEMS device, wherein the escort ring encircles the contact plug.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: November 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Ying Tsai, Hung-Hua Lin, Lung Yuan Pan, Yao-Te Huang, Hsin-Ting Huang, Jung-Huei Peng
  • Publication number: 20150239732
    Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a MEMS device in a MEMS area, where a first metal layer is connected to a first metal connect adjacent the MEMS area and a cap is over the MEMS area to vacuum seal the MEMS area. A first wafer portion is over and bonded to the first metal layer which connects the first metal connect to a first I/O port using metal routing. The first metal layer and the first wafer portion bond requires 10% less bonding area than a bond not including the first metal layer. The semiconductor arrangement including the first metal layer has increased conductivity and requires less processing than an arrangement that requires a dopant implant to connect a first metal connect to a first I/O port and has a better vacuum seal due to a reduction in outgassing.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 27, 2015
    Inventors: Hsin-Ting Huang, Hsiang-Fu Chen, Wen-Chuan Tai, Chia-Ming Hung, Shao-Chi Yu, Hung-Hua Lin, Yuan-Chih Hsieh
  • Publication number: 20150102432
    Abstract: The present disclosure relates to a method of gettering that provides for a high efficiency gettering process by depositing a gettering material on a roughened substrate surface, and an associated apparatus. In some embodiments, the method is performed by providing a substrate into a processing chamber having residual gases. One or more cavities are formed in the substrate at locations between bonding areas on a top surface of the substrate. Respective cavities have roughened interior surfaces that vary in a plurality of directions. A getter layer is deposited into the one or more cavities. The roughened interior surfaces of the one or more cavities enable the substrate to more effectively absorb the residual gases, thereby increasing the efficiency of the gettering process.
    Type: Application
    Filed: October 15, 2013
    Publication date: April 16, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yuan-Chih Hsieh, Li-cheng Chu, Hung-Hua Lin, Chih-Jen Chan, Lan-Lin Chao
  • Publication number: 20150044759
    Abstract: A biological sensing structure includes a mesa integrally connected a portion of a substrate, wherein the mesa has a top surface and a sidewall surface adjacent to the top surface. The biological sensing structure includes a first light reflecting layer over the top surface and the sidewall surface of the mesa. The biological sensing structure includes a filling material surrounding the mesa, wherein the mesa protrudes from the filling material. The biological sensing structure includes a stop layer over the filling material and a portion of the first light reflecting layer. The biological sensing structure includes a second light reflecting layer over a portion of the stop layer and a portion of the top surface of the mesa. The biological sensing structure includes an opening in the second light reflecting layer to partially expose the top surface of the mesa.
    Type: Application
    Filed: September 19, 2014
    Publication date: February 12, 2015
    Inventors: Hung-Hua LIN, Li-Cheng CHU, Ming-Tung WU, Yuan-Chih HSIEH, Lan-Lin CHAO, Chia-Shiung TSAI
  • Patent number: 8945344
    Abstract: Systems and methods of separating bonded wafers are disclosed. In one embodiment, a system for separating bonded wafers includes a support for the bonded wafers and means for applying a sheer force to the bonded wafers. The system also includes means for applying a vacuum to the bonded wafers.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai
  • Publication number: 20150031159
    Abstract: A device includes a substrate, a routing conductive line over the substrate, a dielectric layer over the routing conductive line, and an etch stop layer over the dielectric layer. A Micro-Electro-Mechanical System (MEMS) device has a portion over the etch stop layer. A contact plug penetrates through the etch stop layer and the dielectric layer. The contact plug connects the portion of the MEMS device to the routing conductive line. An escort ring is disposed over the etch stop layer and under the MEMS device, wherein the escort ring encircles the contact plug.
    Type: Application
    Filed: September 12, 2014
    Publication date: January 29, 2015
    Inventors: Shang-Ying Tsai, Hung-Hua Lin, Lung Yuan Pan, Yao-Te Huang, Hsin-Ting Huang, Jung-Huei Peng
  • Patent number: 8905293
    Abstract: A bond free of an anti-stiction layer and bonding method is disclosed. An exemplary method includes forming a first bonding layer; forming an interlayer over the first bonding layer; forming an anti-stiction layer over the interlayer; and forming a liquid from the first bonding layer and interlayer, such that the anti-stiction layer floats over the first bonding layer. A second bonding layer can be bonded to the first bonding layer while the anti-stiction layer floats over the first bonding layer, such that a bond between the first and second bonding layers is free of the anti-stiction layer.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Li-Cheng Chu, Hung-Hua Lin, Shang-Ying Tsai, Yuan-Chih Hsieh, Jung-Huei Peng, Lan-Lin Chao, Chia-Shiung Tsai, Chun-Wen Cheng
  • Patent number: 8853801
    Abstract: A device includes a substrate, a routing conductive line over the substrate, a dielectric layer over the routing conductive line, and an etch stop layer over the dielectric layer. A Micro-Electro-Mechanical System (MEMS) device has a portion over the etch stop layer. A contact plug penetrates through the etch stop layer and the dielectric layer. The contact plug connects the portion of the MEMS device to the routing conductive line. An escort ring is disposed over the etch stop layer and under the MEMS device, wherein the escort ring encircles the contact plug.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Ying Tsai, Jung-Huei Peng, Hsin-Ting Huang, Yao-Te Huang, Lung Yuan Pan, Hung-Hua Lin
  • Patent number: 8846129
    Abstract: A method of forming of biological sensing structures including a portion of a substrate is recessed to form a plurality of mesas in the substrate. Each of the plurality of mesas has a top surface and a sidewall surface. A first light reflecting layer is deposited over the top surface and the sidewall surface of each mesa. A filling material is formed over a first portion of the first light reflecting layer. A stop layer is deposited over the filling material and a second portion of the first light reflecting layer. A sacrificial layer is formed over the stop layer and is planarized exposing the stop layer. A first opening is formed in the stop layer and the first light reflecting layer. A second light reflecting layer is deposited over the first opening. A second opening is formed in the second light reflecting layer.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Hua Lin, Li-Cheng Chu, Ming-Tung Wu, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai
  • Patent number: 8802538
    Abstract: Methods for hybrid wafer bonding. In an embodiment, a method is disclosed that includes forming a metal pad layer in a dielectric layer over at least two semiconductor substrates; performing chemical mechanical polishing on the semiconductor substrates to expose a surface of the metal pad layer and planarize the dielectric layer to form a bonding surface on each semiconductor substrate; performing an oxidation process on the at least two semiconductor substrates to oxidize the metal pad layer to form a metal oxide; performing an etch to remove the metal oxide, recessing the surface of the metal pad layer from the bonding surface of the dielectric layer of each of the at least two semiconductor substrates; physically contacting the bonding surfaces of the at least two semiconductor substrates; and performing a thermal anneal to form bonds between the metal pads of the semiconductor substrates. Additional methods are disclosed.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Jen-Cheng Liu, Xiaomeng Chen, Xin-Hua Huang, Hung-Hua Lin, Lan-Lin Chao, Chia-Shiung Tsai
  • Patent number: 8735260
    Abstract: The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a bonding pad on a first substrate; forming wiring pads on the first substrate; forming a protection material layer on the first substrate, on sidewalls and top surfaces of the wiring pads, and on sidewalls of the bonding pad, such that a top surface of the bonding pad is at least partially exposed; bonding the first substrate to a second substrate through the bonding pad; opening the second substrate to expose the wiring pads; and removing the protection material layer.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Ying Tsai, Jung-Huei Peng, Hsin-Ting Huang, Hung-Hua Lin, Ming-Tung Wu, Ping-Yin Liu, Yao-Te Huang, Yuan-Chih Hsieh
  • Publication number: 20140138853
    Abstract: A device is described in one embodiment that includes a micro-electro-mechanical systems (MEMS) device disposed on a first substrate and a semiconductor device disposed on a second substrate. A bond electrically connects the MEMS device and the semiconductor device. The bond includes an interface between a first bonding layer including silicon on the first substrate and a second bonding layer including aluminum on the second substrate. The physical interface between the aluminum and silicon (e.g., amorphous silicon) can provide an electrical connection.
    Type: Application
    Filed: January 31, 2014
    Publication date: May 22, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Martin Liu, Richard Chu, Hung-Hua LIn, H. T. Huang, Jung-Huei Peng, Yuan-Chih Hsieh, Lan-Lin, Chun-Wen Cheng, Chia-Shiung Tsai
  • Patent number: 8647962
    Abstract: The present disclosure provides a method of bonding a plurality of substrates. In an embodiment, a first substrate includes a first bonding layer. The second substrate includes a second bonding layer. The first bonding layer includes silicon; the second bonding layer includes aluminum. The first substrate and the second substrate are bonded forming a bond region having an interface between the first bonding layer and the second bonding layer. A device having a bonding region between substrates is also provided. The bonding region includes an interface between a layer including silicon and a layer including aluminum.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: February 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Martin Liu, Richard Chu, Hung Hua Lin, Hsin-Ting Huang, Jung-Huei Peng, Yuan-Chih Hsieh, Lan-Lin Chao, Chun-Wen Cheng, Chia-Shiung Tsai
  • Publication number: 20140020818
    Abstract: Systems and methods of separating bonded wafers are disclosed. In one embodiment, a system for separating bonded wafers includes a support for the bonded wafers and means for applying a sheer force to the bonded wafers. The system also includes means for applying a vacuum to the bonded wafers.
    Type: Application
    Filed: July 20, 2012
    Publication date: January 23, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai
  • Patent number: 8633086
    Abstract: A method for forming a support structure for supporting and handling a semiconductor wafer containing vertical FETs formed at the front surface thereof is provided. In one embodiment, a semiconductor wafer is provided having a front surface and a rear surface, wherein the front surface comprises one or more dies separated by dicing lines. The wafer is thinned to a predetermined thickness. A plurality of patterned metal features are formed on a thinned rear surface to provide support for the wafer, wherein each of the plurality of patterned metal features covers substantially one die, leaving the dicing lines substantially uncovered. The wafer is thereafter diced along the dicing lines to separate the one or more dies for later chip packaging.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: January 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Alex Kalnitsky, Hsiao-Chin Tuan, Liang-Kai Han, Uway Tseng, Yuan-Chih Hsieh, Hung-Hua Lin
  • Publication number: 20130277770
    Abstract: A device includes a substrate, a routing conductive line over the substrate, a dielectric layer over the routing conductive line, and an etch stop layer over the dielectric layer. A Micro-Electro-Mechanical System (MEMS) device has a portion over the etch stop layer. A contact plug penetrates through the etch stop layer and the dielectric layer. The contact plug connects the portion of the MEMS device to the routing conductive line. An escort ring is disposed over the etch stop layer and under the MEMS device, wherein the escort ring encircles the contact plug.
    Type: Application
    Filed: April 19, 2012
    Publication date: October 24, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Ying Tsai, Jung-Huei Peng, Hsin-Ting Huang, Yao-Te Huang, Lung Yuan Pan, Hung-Hua Lin
  • Publication number: 20130208371
    Abstract: A method of forming of biological sensing structures including a portion of a substrate is recessed to form a plurality of mesas in the substrate. Each of the plurality of mesas has a top surface and a sidewall surface. A first light reflecting layer is deposited over the top surface and the sidewall surface of each mesa. A filling material is formed over a first portion of the first light reflecting layer. A stop layer is deposited over the filling material and a second portion of the first light reflecting layer. A sacrificial layer is formed over the stop layer and is planarized exposing the stop layer. A first opening is formed in the stop layer and the first light reflecting layer. A second light reflecting layer is deposited over the first opening. A second opening is formed in the second light reflecting layer.
    Type: Application
    Filed: February 13, 2012
    Publication date: August 15, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Hua LIN, Li-Cheng CHU, Ming-Tung WU, Yuan-Chih HSIEH, Lan-Lin CHAO, Chia-Shiung TSAI
  • Patent number: 8405169
    Abstract: A device is provided which includes a transparent substrate. An opaque layer is disposed on the transparent substrate. A conductive layer disposed on the opaque layer. The opaque layer and the conductive layer form a handling layer, which may be used to detect and/or align the transparent wafer during fabrication processes. In an embodiment, the conductive layer includes a highly-doped silicon layer. In an embodiment, the opaque layer includes a metal. In embodiment, the device may include a MEMs device.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: March 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ren Cheng, Yi-Hsien Chang, Allen Timothy Chang, Ching-Ray Chen, Li-Cheng Chu, Hung-Hua Lin, Yuan-Chih Hsieh, Lan-Lin Chao
  • Publication number: 20120149152
    Abstract: The present disclosure provide a method of manufacturing a microelectronic device. The method includes forming a bonding pad on a first substrate; forming wiring pads on the first substrate; forming a protection material layer on the first substrate, on sidewalls and top surfaces of the wiring pads, and on sidewalls of the bonding pad, such that a top surface of the bonding pad is at least partially exposed; bonding the first substrate to a second substrate through the bonding pad; opening the second substrate to expose the wiring pads; and removing the protection material layer.
    Type: Application
    Filed: December 13, 2010
    Publication date: June 14, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Ying Tsai, Jung-Huei Peng, Hsin-Ting Huang, Hung-Hua Lin, Ming-Tung Wu, Ping-Yin Liu, Yao-Te Huang, Yuan-Chih Hsieh