Patents by Inventor Hung-Jen Liao

Hung-Jen Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220293492
    Abstract: A memory macro structure includes a first memory array, a second memory array, a cell activation circuit coupled to the first and second memory arrays and positioned between the first and second memory arrays, a control circuit coupled to the cell activation circuit and positioned adjacent to the cell activation circuit, and a through-silicon via (TSV) extending through one of the cell activation circuit or the control circuit.
    Type: Application
    Filed: March 23, 2021
    Publication date: September 15, 2022
    Inventors: Hidehiro FUJIWARA, Tze-Chiang HUANG, Hong-Chen CHENG, Yen-Huei CHEN, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG, Yun-Han LEE, Lee-Chung LU
  • Publication number: 20220277781
    Abstract: A memory circuit includes a NAND logic gate, a first N-type transistor, a second N-type transistor, a first inverter and a first latch. The NAND logic gate is configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The first N-type transistor is coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The second N-type transistor is coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The first inverter is coupled to the NAND logic gate, and configured to output a data signal inverted from the first signal. The first latch is coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.
    Type: Application
    Filed: April 20, 2021
    Publication date: September 1, 2022
    Inventors: Yi-Tzu CHEN, Ching-Wei WU, Hau-Tai SHIEH, Hung-Jen LIAO, Fu-An WU, He-Zhou WAN, XiuLi YANG
  • Publication number: 20220278111
    Abstract: An apparatus includes memory cells. A first memory cell of the memory cells includes a first write port laid out in a first doping region and a first read port laid out in a second doping region. The first read port is separated from the first write port by a second write port of a second memory cell of the memory cells.
    Type: Application
    Filed: August 24, 2021
    Publication date: September 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hidehiro FUJIWARA, Yi-Hsin NIEN, Hung-Jen LIAO
  • Patent number: 11423977
    Abstract: The disclosed write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Hidehiro Fujiwara, Chih-Yu Lin, Sahil Preet Singh, Hsien-Yu Pan, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 11423974
    Abstract: A method of fabricating (a distributed write driving arrangement for a semiconductor memory device) includes: forming bit cells and a local write driver in a first device layer; forming a local write bit (LWB) line and a local write bit_bar (LWB_bar) line in a first metallization layer; connecting each of the bit cells correspondingly between the LWB and LWB_bar lines; connecting the local write driver to the LWB line and the LWB_bar line; forming a global write bit (GWB) line and a global write bit_bar (GWBL_bar) line in a second metallization layer; connecting the GWB line to the LWB line; connecting the GWB line and the GWBL_bar line to the corresponding LWB line and LWB_bar line; forming a global write driver in a second device layer; and connecting the global write driver to the GWB line and the GWBL_bar line.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen
  • Patent number: 11423978
    Abstract: A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sahil Preet Singh, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 11404114
    Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Patent number: 11404115
    Abstract: The disclosure introduces a write assist scheme that boost the word line of a selected memory cell by using a parasitic capacitor element coupled between the word line and a bit line of at least one unselected memory cell. The SRAM includes a word line, a first bit line, a second bit line, a first memory cell coupled to the first bit line and the word line, a second memory cell coupled to the second bit line and the word line, and a write assist circuit coupled to the second bit line. The write assist circuit is configured to clamp the second bit line to the word line during a write operation of the first memory cell.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Yen-Huei Chen
  • Patent number: 11398275
    Abstract: A circuit includes a memory array, a write circuit configured to store data in memory cells of the memory array, a read circuit configured to retrieve the stored data from the memory cells of the memory array, and a computation circuit configured to perform one or more logic operations on the retrieved stored data. The memory array is positioned between the write circuit and the read circuit.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: July 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Hidehiro Fujiwara
  • Patent number: 11394837
    Abstract: A system and a method using matrix barcode information to process documents are provided. A document-processing apparatus generates matrix barcode information and establishes a wireless link with a mobile apparatus through the matrix barcode information. When the document-processing apparatus establishes the wireless link with the mobile apparatus, the document-processing apparatus creates a file transfer zone, performs a corresponding automatic document-processing action, such as scanning or printing, according to a driving command received from the mobile apparatus, and exchanges the generated image information with the mobile apparatus through the file transfer zone. Given the matrix barcode information, the document-processing apparatus can be directly controlled by the mobile apparatus to achieve direct information exchange and enhanced efficiency and security of the document-processing system.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: July 19, 2022
    Assignee: AVISION INC.
    Inventors: Chun-Cheih Liao, Hung-Jen Lin, Chun-Ping Huang
  • Publication number: 20220199145
    Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.
    Type: Application
    Filed: March 4, 2022
    Publication date: June 23, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao
  • Patent number: 11361812
    Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao
  • Publication number: 20220139450
    Abstract: The disclosure introduces a write assist scheme that boost the word line of a selected memory cell by using a parasitic capacitor element coupled between the word line and a bit line of at least one unselected memory cell. The SRAM includes a word line, a first bit line, a second bit line, a first memory cell coupled to the first bit line and the word line, a second memory cell coupled to the second bit line and the word line, and a write assist circuit coupled to the second bit line. The write assist circuit is configured to clamp the second bit line to the word line during a write operation of the first memory cell.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Yen-Huei Chen
  • Publication number: 20220130446
    Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.
    Type: Application
    Filed: October 27, 2020
    Publication date: April 28, 2022
    Inventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao
  • Patent number: 11301148
    Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Hung-Jen Liao, Jung-Ping Yang, Jonathan Tsung-Yung Chang, Wei Min Chan, Yen-Huei Chen, Yangsyu Lin, Chien-Chen Lin
  • Publication number: 20220083089
    Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.
    Type: Application
    Filed: November 24, 2021
    Publication date: March 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu, Yen-Huei Chen, Hung-Jen Liao, Chiting Cheng
  • Publication number: 20220068355
    Abstract: The disclosure is directed to a memory circuit, an electronic device, and a method of operating the memory circuit. According to an exemplary embodiment, the disclosure is directed to a memory circuit which includes not limited to a voltage equalizing circuit configured to equalize and pre-charge a first data line and a second data line to a reference voltage, a sense amplifier circuit configured to sense a binary data based on a relative voltage between the first data line and the second data line, a read-out latch circuit configured to receive the binary data which is to be transmitted to an external controller, and a write circuit configured to receive a first signal of the first data line and a second signal of the second data line so as to write the first signal to a first bit line and the second signal to a second bit line.
    Type: Application
    Filed: August 30, 2020
    Publication date: March 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hua-Hsin Yu, Cheng-Hung Lee, Hung-Jen Liao, Hau-Tai Shieh
  • Patent number: 11264081
    Abstract: The disclosure is directed to a memory circuit, an electronic device, and a method of operating the memory circuit. According to an exemplary embodiment, the disclosure is directed to a memory circuit which includes not limited to a voltage equalizing circuit configured to equalize and pre-charge a first data line and a second data line to a reference voltage, a sense amplifier circuit configured to sense a binary data based on a relative voltage between the first data line and the second data line, a read-out latch circuit configured to receive the binary data which is to be transmitted to an external controller, and a write circuit configured to receive a first signal of the first data line and a second signal of the second data line so as to write the first signal to a first bit line and the second signal to a second bit line.
    Type: Grant
    Filed: August 30, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manfacturing Company, Ltd.
    Inventors: Hua-Hsin Yu, Cheng-Hung Lee, Hung-Jen Liao, Hau-Tai Shieh
  • Patent number: 11199866
    Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu, Yen-Huei Chen, Hung-Jen Liao, Chiting Cheng
  • Patent number: 11200946
    Abstract: Systems and methods for a bit-cell are presented. The bit-cell comprises a read-port circuit and a write-port circuit. The read-port circuit comprises four transistors, wherein the read-port circuit is activated by a first threshold voltage. The write-port circuit comprises eight transistors, wherein the write-port circuit is activated by a second threshold voltage. The write-port circuit is coupled to the read-port circuit. The first threshold voltage and the second threshold voltage may be different and may be provided by a single supply voltage.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mahmut Sinangil, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Yen-Ting Lin