Patents by Inventor Hung-Jen Liao

Hung-Jen Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SRAM cell for interleaved wordline scheme
    Patent number: 10770131
    Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil
  • Semiconductor device including distributed write driving arrangement and method of operating same
    Patent number: 10755768
    Abstract: A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells; each of the bit cells including a latch circuit and first and second pass gates connecting the corresponding LWB and LWB_bar lines to the latch circuit; and a distributed write driving arrangement. The distributed write driving arrangement includes: a global write driver including a first inverter connected between the GWB line and the LWB line, and a second inverter connected between the GWB_bar line and the LWB_bar line; and a local write driver included at an interior of each segment, each local write driver including a third inverter connected between the GWB line and the LWB line; and a fourth inverter connected between the GWB_bar line and the LWB_bar line.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen
  • Static random access memory with write assist circuit
    Patent number: 10734066
    Abstract: A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hidehiro Fujiwara, Chih-Yu Lin, Sahil Preet Singh, Hsien-Yu Pan, Yen-Huei Chen, Hung-Jen Liao
  • LEVEL SHIFTER
    Publication number: 20200235724
    Abstract: A level shifter includes: an input terminal configured to receive an input signal in a first voltage domain; a first output terminal; a second output terminal; a first inverter configured to receive and shift the input signal to a first output signal at the first output terminal in a second voltage domain higher than the first voltage domain in response to a logical high state of an enable signal in the first voltage domain; a second inverter configured to receive and shift a complement of the input signal to a second output signal at the second output terminal in the second voltage domain in response to the logical high state; a pair of NMOS sensing transistors; a PMOS transistor configured to equalize the first output signal and the second output signal in response to a logical low state of the enable signal.
    Type: Application
    Filed: April 8, 2020
    Publication date: July 23, 2020
    Inventors: Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao, Hau-Tai Shieh
  • Memory cell
    Patent number: 10714181
    Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Chien-Chen Lin
  • Power switch control for dual power supply
    Patent number: 10685686
    Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yu-Hao Hsu
  • Static random access memory circuit
    Patent number: 10685704
    Abstract: A static random access memory (SRAM) includes a bit cell that includes a p-type pass gate, a bit information path connected to the bit cell by the p-type pass gate, and a write multiplexer connected to the bit information path. The write multiplexer includes a p-type transistor configured to selectively couple the bit information path to a flip-flop.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Wu, Wei Min Chan, Yen-Huei Chen, Hung-Jen Liao, Ping-Wei Wang
  • MEMORY MACRO AND METHOD OF OPERATING THE SAME
    Publication number: 20200176037
    Abstract: A memory macro includes a first memory cell array, a first tracking circuit, a first and a second transistor. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first control signal, a second set of memory cells configured as a first set of pull-down cells responsive to a second control signal, and a first tracking bit line extending over the first tracking circuit. The second control signal is inverted from the first control signal. At least the first set of pull-down cells or the first set of loading cells is configured to track a memory cell of the first memory cell array. The first and second transistor are coupled to the first tracking bit line, and are configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third control signal.
    Type: Application
    Filed: February 6, 2020
    Publication date: June 4, 2020
    Inventors: Chien-Kuo SU, Cheng Hung LEE, Chiting CHENG, Hung-Jen LIAO, Jonathan Tsung-Yung CHANG, Yen-Huei CHEN, Pankaj AGGARWAL, Jhon Jhy LIAW
  • Memory circuit having resistive device coupled with supply voltage line
    Patent number: 10672776
    Abstract: A memory circuit including: a first column of memory cells, each memory cell of the first column including a first supply segment; a first supply voltage line in a first conductive layer, the first supply voltage line being made of at least the first supply segments of the first column; a second supply voltage line; a first resistive device electrically connecting the first and second supply voltage lines, and being located in a via layer; a first material, from which the first resistive device is formed, being different than a second material from which a first type of via plug in the via layer is formed; and a supply voltage source electrically coupled with first supply voltage line through one or more conductive paths, and the second supply voltage line and the first resistive device being in a lowest resistance path of the one or more conductive paths.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Huei Chen, Hung-Jen Liao, Chih-Yu Lin, Jonathan Tsung-Yung Chang, Wei-Cheng Wu
  • MEMORY DEVICE WITH STRAP CELLS
    Publication number: 20200152242
    Abstract: A device includes a memory array. The memory array includes a first sub-bank, a first strap cell coupled to the first sub-bank, and a first continuous data line. The first continuous data line includes a first portion and a second portion coupled to the first sub-bank via the first strap cell. The first portion of the first continuous data line is disposed above the first strap cell and the second portion of the first continuous data line is disposed above the first portion of the first continuous data line.
    Type: Application
    Filed: January 15, 2020
    Publication date: May 14, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung CHANG, Cheng-Hung LEE, Chi-Ting CHENG, Hung-Jen LIAO, Jhon-Jhy LIAW, Yen-Huei CHEN
  • Level shifter
    Patent number: 10651832
    Abstract: A level shifter is configured to receive an input signal in a first voltage domain and output an output signal in a second voltage domain. An input terminal is configured to receive an input signal in a first voltage domain. A first sensing circuit is configured to shift the input signal from the first voltage domain to the second voltage domain, and a second sensing circuit is configured to shift the input signal from the first voltage domain to the second voltage domain. An enable circuit is configured to equalize a voltage level of first and second output signals at respective first and second output terminals in response to an enable signal. The first and second sensing circuits are configured output complementary output signals in the second voltage domain at the first and second output terminals in response to the enable signal and the input signal.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, LTD.
    Inventors: Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao, Hau-Tai Shieh
  • Write Assist for a Memory Device and Methods of Forming the Same
    Publication number: 20200143875
    Abstract: A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 7, 2020
    Inventors: Sahil Preet Singh, Yen-Huei Chen, Hung-Jen Liao
  • Semiconductor Memory Device Using Shared Data Line for Read/Write Operation
    Publication number: 20200111526
    Abstract: A semiconductor memory device comprising a plurality of memory cells configured to store digital data and an input multiplexer configured to enable the selection of a particular memory cell from the plurality of memory cells. The semiconductor memory device further comprises a read/write driver circuit configured to read data from the selected memory cell and write data to the selected memory cell, and a write logic block configured to provide logical control to the read/write driver circuit for writing data to the selected of memory cell. The read/write driver circuit may be coupled to the read/write input multiplexer by a data line and an inverted data line and the read and the write operations to the selected memory cell occur over the same data line and inverted data line.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 9, 2020
    Inventors: Chien-Yuan Chen, Che-Ju Yeh, Hau-Tai Shieh, Cheng-Hung Lee, Hung-Jen Liao, Sahil Preet Singh, Manish Arora, Hemant Patel, Li-Wen Wang
  • CONFIGURABLE MEMORY STORAGE SYSTEM
    Publication number: 20200081636
    Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.
    Type: Application
    Filed: November 15, 2019
    Publication date: March 12, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hao HSU, Cheng Hung LEE, Chen-Lin YANG, Chiting CHENG, Fu-An WU, Hung-Jen LIAO, Jung-Ping YANG, Jonathan Tsung-Yung CHANG, Wei Min CHAN, Yen-Huei CHEN, Yangsyu LIN, Chien-Chen LIN
  • MEMORY READ STABILITY ENHANCEMENT WITH SHORT SEGMENTED BIT LINE ARCHITECTURE
    Publication number: 20200075092
    Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.
    Type: Application
    Filed: November 7, 2019
    Publication date: March 5, 2020
    Inventors: Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh
  • LEVEL SHIFTER
    Publication number: 20200052678
    Abstract: A level shifter is configured to receive an input signal in a first voltage domain and output an output signal in a second voltage domain. An input terminal is configured to receive an input signal in a first voltage domain. A first sensing circuit is configured to shift the input signal from the first voltage domain to the second voltage domain, and a second sensing circuit is configured to shift the input signal from the first voltage domain to the second voltage domain. An enable circuit is configured to equalize a voltage level of first and second output signals at respective first and second output terminals in response to an enable signal. The first and second sensing circuits are configured output complementary output signals in the second voltage domain at the first and second output terminals in response to the enable signal and the input signal.
    Type: Application
    Filed: April 19, 2019
    Publication date: February 13, 2020
    Inventors: Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao, Hau-Tai Shieh
  • Memory macro and method of operating the same
    Patent number: 10559333
    Abstract: A memory macro includes a first memory cell array, first tracking circuit, first pre-charge circuit coupled to a first end of the first tracking bit line and a second pre-charge circuit coupled to a second end of the first tracking bit line. The first tracking circuit includes a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals, a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, and a first tracking bit line. The first set of pull-down cells and first set of loading cells are configured to track a memory cell of the first memory cell array. The first and second pre-charge circuit are configured to charge the first tracking bit line to a voltage level responsive to a third set of control signals.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: February 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Kuo Su, Cheng Hung Lee, Chiting Cheng, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Pankaj Aggarwal, Jhon Jhy Liaw
  • Memory device with strap cells
    Patent number: 10541007
    Abstract: A device includes a memory array. The memory array includes a first sub-bank, a second sub-bank, a strap cell and a continuous data line. The strap cell is arranged between the first sub-bank and the second sub-bank. The continuous data line includes a first portion coupled to the first sub-bank and a second portion disposed across the second sub-bank. The first portion of the continuous data line and the second portion of the continuous data line are disposed at separate layers above the strap cell.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: January 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jonathan Tsung-Yung Chang, Cheng-Hung Lee, Chi-Ting Cheng, Hung-Jen Liao, Jhon-Jhy Liaw, Yen-Huei Chen
  • MEMORY CELL AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20200020699
    Abstract: A memory cell includes a first and second pull up transistor, a first and second pass gate transistor and a metal contact. The first pull up transistor has a first active region extending in a first direction. The first pass gate transistor has a second active region extending in the first direction, and being separated from the first active region in a second direction. The second active region is adjacent to the first active region. The second pass gate transistor is coupled to the second pull up transistor. The metal contact extends in the second direction, and extends from the first active region to the second active region. The metal contact couples drains of the first pull up transistor and the first pass gate transistor. The first and second pass gate transistors and the first and second pull up transistors are part of a four transistor memory cell.
    Type: Application
    Filed: June 28, 2019
    Publication date: January 16, 2020
    Inventors: Hidehiro FUJIWARA, Hung-Jen LIAO, Hsien-Yu PAN, Chih-Yu LIN, Yen-Huei CHEN, Yasutoshi OKUNO
  • POWER SWITCH CONTROL FOR DUAL POWER SUPPLY
    Publication number: 20200020363
    Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yu-Hao Hsu