Abstract: A structure including a redistribution structure comprising dielectric layers and conductive layers alternately stacked is provided, wherein a dielectric layer among the dielectric layers of the redistribution structure comprises a first surface, a conductive layer among the conductive layers of the redistribution structure comprising a second surface, and the conductive layer comprises a wiring layer and a seed layer; and an under-bump metallization (UBM) layer comprises a third surface, a fourth surface opposite to the third surface, and a sidewall surface extending from the third surface to the fourth surface, wherein a portion of the seed layer is between the wiring layer and the UBM layer, and the UBM is in contact with the dielectric layer

Abstract: A photoresist apparatus and a method are provided. The photoresist apparatus includes a pre-baking apparatus. The pre-baking apparatus includes: a hot-plate, a first cover over the hot-plate, a second cover over the first cover, a first heating element extending along a topmost surface of the first cover, and a second heating element extending along a topmost surface of the second cover.

Abstract: Semiconductor package includes substrate, first barrier layer, second barrier layer, routing via, first routing pattern, second routing pattern, semiconductor die. Substrate has through hole with tapered profile, wider at frontside surface than at backside surface of substrate. First barrier layer extends on backside surface. Second barrier layer extends along sidewalls of through hole and on frontside surface. Routing via fills through hole and is separated from sidewalls of through hole by at least second barrier layer. First routing pattern extends over first barrier layer on backside surface and over routing via. First routing pattern is electrically connected to end of routing via and has protrusion protruding towards end of routing via in correspondence of through hole. Second routing pattern extends over second barrier layer on frontside surface. Second routing pattern directly contacts another end of routing via. Semiconductor die is electrically connected to routing via by first routing pattern.

Abstract: A semiconductor package includes a substrate, a composite seed-barrier layer, a routing via, and a semiconductor die. The substrate has a through hole formed therethrough. The composite seed-barrier layer extends on sidewalls of the through hole and includes a first barrier layer, a seed layer, and a second barrier layer sequentially stacked on the sidewalls of the through hole. The routing via fills the through hole and is separated from the substrate by the composite seed-barrier layer. The semiconductor die is electrically connected to the routing via. Along the sidewalls of the through holes, at a level height corresponding to half of a total thickness of the substrate, the seed layer is present as inclusions of seed material surrounded by barrier material of the first barrier layer and the second barrier layer.

Abstract: An integrated fan-out (InFO) package includes a die, a plurality of conductive structures aside the die, an encapsulant laterally encapsulating the die and the conductive structure, and a redistribution structure. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks. The routing patterns and the conductive vias are electrically connected to the die and the conductive structures. The alignment marks surround the routing patterns and the conductive vias. The alignment marks are electrically insulated from the die and the conductive structures. At least one of the alignment marks is in physical contact with the encapsulant, and vertical projections of the alignment marks onto the encapsulant have an offset from one another.

Abstract: A method includes the following steps. A photoresist is exposed to a first light-exposure through a first mask, wherein the first mask includes a first stitching region, and a portion of the photoresist corresponding to a portion of the first stitching region is unexposed during the first light-exposure. The photoresist is exposed to a second light-exposure through a second mask, wherein the second mask includes a second stitching region and a functional feature in the second stitching region, and the portion of the photoresist is exposed by the functional feature during the second light-exposure.

Abstract: A package includes a die and a redistribution structure. The die has an active surface and is wrapped around by an encapsulant. The redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.

Abstract: A device includes a molding compound, a plurality of through vias, a seal ring structure, and a protection layer. The plurality of through vias are embedded in the molding compound. The seal ring structure is over the molding compound and surrounds the through vias in a top view. The protection layer covers the seal ring and extends toward the molding compound in a cross-sectional view.

Abstract: A method of manufacturing a semiconductor device includes applying a polymer mixture over a substrate, exposing and developing at least a portion of the polymer mixture to form a developed dielectric, and curing the developed dielectric to form a dielectric layer. The polymer mixture includes a polymer precursor, a photosensitizer, and a solvent. The polymer precursor may be a polyamic acid ester.

Abstract: A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

Abstract: A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler.

Abstract: A package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer.

Abstract: In an embodiment, a device includes: an interconnect structure including a first contact pad, a second contact pad, and an alignment mark; a light emitting diode including a cathode and an anode, the cathode connected to the first contact pad; an encapsulant encapsulating the light emitting diode; a first conductive via extending through the encapsulant, the first conductive via including a first seed layer, the first seed layer contacting the second contact pad; a second conductive via extending through the encapsulant, the second conductive via including a second seed layer, the first seed layer and the second seed layer including a first metal; and a hardmask layer between the second seed layer and the alignment mark, the hardmask layer including a second metal, the second metal different from the first metal.

Abstract: A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.

Abstract: A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

Abstract: A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.

Abstract: A single layer process is utilized to reduce swing effect interference and reflection during imaging of a photoresist. An anti-reflective additive is added to a photoresist, wherein the anti-reflective additive has a dye portion and a reactive portion. Upon dispensing the reactive portion will react with underlying structures to form an anti-reflective coating between the underlying structure and a remainder of the photoresist. During imaging, the anti-reflective coating will either absorb the energy, preventing it from being reflected, or else modify the optical path of reflection, thereby helping to reduce interference caused by the reflected energy.

Abstract: An integrated circuit package and a method of forming the same are provided. A method includes forming a first redistribution layer over a carrier, the first redistribution layer including a contact pad and a bond pad. A conductive pillar is formed over the contact pad. A backside surface of an integrated circuit die is attached to the bond pad using a solder joint. An encapsulant is formed along a sidewall of the conductive pillar and a sidewall of the integrated circuit die, a front-side surface of the integrated circuit die being substantially level with a topmost surface of the encapsulant and a topmost surface of the conductive pillar. A second redistribution layer is formed over the front-side surface of the integrated circuit die, the topmost surface of the encapsulant and the topmost surface of the conductive pillar.

Abstract: A photoresist apparatus and a method are provided. The photoresist apparatus includes a pre-baking apparatus. The pre-baking apparatus includes: a hot-plate, a first cover over the hot-plate, a second cover over the first cover, a first heating element extending along a topmost surface of the first cover, and a second heating element extending along a topmost surface of the second cover.

Abstract: A semiconductor package includes a die and an encapsulant. The die has an active surface and an opposite backside surface. The encapsulant wraps around the die and has a recess reaching the backside surface. A span of the recess differs from a span of the backside surface and a span of the encapsulant.