Patents by Inventor Hung Li

Hung Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240047873
    Abstract: An antenna structure includes a metal mechanism element, a ground element, a feeding radiation element, and a dielectric substrate. The metal mechanism element has a slot. The ground element is coupled to the metal mechanism element. The feeding radiation element has a feeding point. The feeding radiation element is coupled to the ground element. The dielectric substrate has a first surface and a second surface which are opposite to each other. The feeding radiation element is disposed on the first surface of the dielectric substrate. The second surface of the dielectric substrate is adjacent to the metal mechanism element. The slot of the metal mechanism element is excited to generate a first frequency band and a second frequency band. The feeding radiation element is excited to generate a third frequency band. The ground element further includes a first protruding portion and a second protruding portion.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 8, 2024
    Inventors: Po-Yen CHEN, Kuan-Hung LI
  • Publication number: 20240047526
    Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate and spaced apart from each other in a first direction. The semiconductor structure further includes a gate structure wrapping around the nanostructures and a semiconductor layer attached to the nanostructures in a second direction different from the first direction. The semiconductor structure further includes inner spacers sandwiched between the semiconductor layer and the gate structure in the second direction and a silicide layer formed over the semiconductor layer. In addition, a first portion of the semiconductor layer is sandwiched between the inner spacers and the silicide layer in the second direction.
    Type: Application
    Filed: October 16, 2023
    Publication date: February 8, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching CHENG, I-Sheng CHEN, Tzu-Chiang CHEN, Shih-Syuan HUANG, Hung-Li CHIANG
  • Patent number: 11894435
    Abstract: A semiconductor device a method of forming the same are provided. A semiconductor device includes a gate stack over a substrate. A first dielectric layer is over the gate stack. The first dielectric layer includes a first material. A second dielectric layer is over the first dielectric layer. The second dielectric layer includes a second material different from the first material. A first conductive feature is adjacent the gate stack. A second conductive feature is over and in physical contact with a topmost surface of the first conductive feature. A bottommost surface of the second conductive feature is in physical contact with a topmost surface of the second dielectric layer.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Yu Chou, Jr-Hung Li, Tze-Liang Lee
  • Patent number: 11894438
    Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yee-Chia Yeo, Sung-Li Wang, Chi On Chui, Jyh-Cherng Sheu, Hung-Li Chiang, I-Sheng Chen
  • Publication number: 20240032309
    Abstract: A memory device includes a first electrode, a selector layer and a plurality of first work function layers. The first work function layers are disposed between the first electrode and the selector layer, and a work function of the first work function layer increases as the first work function layer becomes closer to the selector layer.
    Type: Application
    Filed: October 3, 2023
    Publication date: January 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Jung-Piao Chiu, Tzu-Chiang Chen, Yu-Sheng Chen, Xinyu BAO
  • Publication number: 20240029917
    Abstract: A method for producing a porous structure electrode with gas permeability and liquid impermeability, includes the following steps: Step 1: mixing a catalytic material having hydrophilicity, a carbon nanotube material, a material with a hydrophilic group, and a carbon black material to form a first slurry, wherein the carbon nanotube material has a specific surface area equal to or greater than the carbon black material; Step 2: mixing the first slurry with an emulsified material to form a second slurry; Step 3: obtaining a film material through a film forming process; Step 4: heating the film material to a first temperature to remove solvent in the film material; Step 5: Repeating steps 3 to 4; and Step 6: heating the film material to a second temperature to remove liquid in the film material, thereby leaving pores in the film material, and allowing the film material to solidify.
    Type: Application
    Filed: July 13, 2023
    Publication date: January 25, 2024
    Inventors: Chia-Hung LI, Kuang-Che LEE, Chien-Yao HUANG, Chun-Hsien TSAI, Ting-Chuan LEE, Chun-Jung TSAI
  • Publication number: 20240021226
    Abstract: In some aspects of the present disclosure, a memory array structure is disclosed. In some embodiments, the memory array structure includes a word array. In some embodiments, the word array stores an N-bit word. In some embodiments, the word array includes a plurality of first memory structures and a plurality of second memory structures. In some embodiments, each first memory structure includes a first transistor and a first memory element. In some embodiments, each second memory structure includes a second transistor and a plurality of second memory elements, each second memory element includes a first end and a second end, the first end of each second memory element is coupled to a corresponding bit line, and the second end of each second memory element is coupled to a first end of the second transistor.
    Type: Application
    Filed: July 12, 2022
    Publication date: January 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang
  • Publication number: 20240021476
    Abstract: In an embodiment, a device includes: a source/drain region over a semiconductor substrate; a dielectric layer over the source/drain region, the dielectric layer including a first dielectric material; an inter-layer dielectric over the dielectric layer, the inter-layer dielectric including a second dielectric material and an impurity, the second dielectric material different from the first dielectric material, a first portion of the inter-layer dielectric having a first concentration of the impurity, a second portion of the inter-layer dielectric having a second concentration of the impurity, the first concentration less than the second concentration; and a source/drain contact extending through the inter-layer dielectric and the dielectric layer to contact the source/drain region, the first portion of the inter-layer dielectric disposed between the source/drain contact and the second portion of the inter-layer dielectric.
    Type: Application
    Filed: January 6, 2023
    Publication date: January 18, 2024
    Inventors: Yu-Lien Huang, Tze-Liang Lee, Jr-Hung Li, Chun-Kai Chen
  • Publication number: 20240019778
    Abstract: Metal-comprising resist layers (for example, metal oxide resist layers), methods for forming the metal-comprising resist layers, and lithography methods that implement the metal-comprising resist layers are disclosed herein that can improve lithography resolution. An exemplary method includes forming a metal oxide resist layer over a workpiece by performing deposition processes to form metal oxide resist sublayers of the metal oxide resist layer over the workpiece and performing a densification process on at least one of the metal oxide resist sublayers. Each deposition process forms a respective one of the metal oxide resist sublayers. The densification process increases a density of the at least one of the metal oxide resist sublayers. Parameters of the deposition processes and/or parameters of the densification process can be tuned to achieve different density profiles, different density characteristics, and/or different absorption characteristics to optimize patterning of the metal oxide resist layer.
    Type: Application
    Filed: August 9, 2023
    Publication date: January 18, 2024
    Inventors: Yi-Chen Kuo, Chih-Cheng Liu, Yen-Yu Chen, Jr-Hung Li, Chi-Ming Yang, Tze-Liang Lee
  • Publication number: 20240021468
    Abstract: In one example aspect, the present disclosure is directed to a method. The method includes receiving a workpiece having a conductive feature over a semiconductor substrate, forming a sacrificial material layer over the conductive feature, removing first portions of the sacrificial material layer to form line trenches and to expose a top surface of the conductive feature in one of the line trenches; forming line features in the line trenches, removing second portions of the sacrificial material layer to form gaps between the line features, and forming dielectric features in the gaps, the dielectric features enclosing an air gap.
    Type: Application
    Filed: August 8, 2023
    Publication date: January 18, 2024
    Inventors: Yu-Hsin Chan, Cai-Ling Wu, Chang-Wen Chen, Po-Hsiang Huang, Yu-Yu Chen, Kuan-Wei Huang, Jr-Hung Li, Jay Chiu, Ting-Kui Chang
  • Publication number: 20240019620
    Abstract: A display device includes a first image generating unit and a first waveguide glass. The first image generating unit is configured to emit first light. The first waveguide glass faces toward the first image generating unit. The first waveguide glass includes a first microstructure, two second microstructures and a third microstructure. The first microstructure is located between two ends at the same side of the two second microstructures. The third microstructure is located between the two second microstructures. The third microstructure has a first grating and a second grating. An extending direction of the first grating is different from an extending direction of the second grating. The second microstructure is configured to receive the first light of the first image generating unit transmitted through the first microstructure and transmit the first light to the third microstructure.
    Type: Application
    Filed: November 30, 2022
    Publication date: January 18, 2024
    Inventors: Han-Sheng NIAN, Ming-Jui WANG, Chih-Chiang CHEN, Chia-Hsin CHUNG, Yu-Cheng SHIH, Wei-Syun WANG, Cheng-Chan WANG, Hsin-Hung LI, Sheng-Ming HUANG
  • Publication number: 20240012241
    Abstract: A head-up display includes an image generating unit and a waveguide glass. The waveguide glass faces toward the image generating unit. The waveguide glass includes a first microstructure, a second microstructure and a third microstructure. The first microstructure has a first width. The second microstructure is adjacent to the first microstructure. The third microstructure is adjacent to the second microstructure. The third microstructure has tiling areas adjacent to each other. A gap between the two adjacent tiling areas is less than half of the first width.
    Type: Application
    Filed: November 29, 2022
    Publication date: January 11, 2024
    Inventors: Han-Sheng NIAN, Seok-Lyul LEE, Ming-Jui WANG, Chih-Chiang CHEN, Chia-Hsin CHUNG, Yu-Cheng SHIH, Cheng-Chan WANG, Hsin-Hung LI, Wei-Syun WANG, Sheng-Ming HUANG
  • Patent number: 11869224
    Abstract: A method and a system for establishing a light source information prediction model are provided. A plurality of training images are captured for a target object. A white object is attached on the target object. True light source information of the training images is obtained according to a color of the white object in each of the training images. A neural network model is trained according to the training images and the true light source information, and a plurality of pieces of predicted light source information is generated according to the neural network model during the training. A learning rate for training the neural network model is adaptively adjusted based on the predicted light source information.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: January 9, 2024
    Assignee: Acer Incorporated
    Inventors: Yi-Jin Huang, Chien-Hung Li, Yin-Hsong Hsu
  • Patent number: 11854895
    Abstract: A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Cheng, Tzu-Ang Chao, Chun-Chieh Lu, Hung-Li Chiang, Tzu-Chiang Chen, Lain-Jong Li
  • Patent number: 11855187
    Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Peng, Chih Chieh Yeh, Chih-Sheng Chang, Hung-Li Chiang, Hung-Ming Chen, Yee-Chia Yeo
  • Patent number: 11854594
    Abstract: A data processing method, a data processing circuit, and a computing apparatus are provided. In the method, data is obtained. A first value of a bit of the data is switched into a second value according to data distribution and an accessing property of memory. The second value of the bit is stored in the memory in response to switching the bit.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltpd.
    Inventors: Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang
  • Patent number: 11844655
    Abstract: A method for estimating a ventricular volume is provided and includes: obtaining a left ventricular mask image corresponding to a heart ultrasound image, where the left ventricular mask image is a binary image; finding 3 reference point pixels in the left ventricular mask image, where each of the reference point pixels has a first value, each of the reference point pixels is surrounded by N surrounding pixels, and the surrounding pixels of each of the reference point pixels include N1 first surrounding pixels with the first value and N2 second surrounding pixels with a second value; estimating a left ventricular volume corresponding to the heart ultrasound image based on the reference point pixels.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: December 19, 2023
    Assignee: Acer Incorporated
    Inventors: Yi-Jin Huang, Chien-Hung Li, Hung-Sheng Hsu
  • Patent number: 11848242
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Li Chiang, Chih-Liang Chen, Tzu-Chiang Chen, I-Sheng Chen, Lei-Chun Chou
  • Patent number: 11843028
    Abstract: Semiconductor devices and methods of fabricating semiconductor devices are provided. The present disclosure provides a semiconductor device that includes a first fin structure and a second fin structure each extending from a substrate; a first gate segment over the first fin structure and a second gate segment over the second fin structure; a first isolation feature separating the first and second gate segments; a first source/drain (S/D) feature over the first fin structure and adjacent to the first gate segment; a second S/D feature over the second fin structure and adjacent to the second gate segment; and a second isolation feature also disposed in the trench. The first and second S/D features are separated by the second isolation feature, and a composition of the second isolation feature is different from a composition of the first isolation feature.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Wen Wu, Fu-Kai Yang, Chen-Ming B. Lee, Mei-Yun Wang, Jr-Hung Li, Bo-Cyuan Lu
  • Patent number: 11837611
    Abstract: Disclosed herein, in some embodiments, is a memory device. The memory device includes a bottom electrode disposed over a substrate and a top electrode disposed over the bottom electrode. An upper surface of the bottom electrode faces away from the substrate. A bottom surface of the top electrode faces the substrate. A data storage layer is arranged between the bottom electrode and the top electrode. At least a portion of the bottom surface of the top electrode does not overlap with any portion of the top surface of the bottom electrode along a first direction parallel to the bottom surface of the top electrode. Furthermore, at least a portion of the top surface of the bottom electrode does not overlap with any portion of the bottom surface of the top electrode along the first direction.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: December 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Jung-Piao Chiu, Tzu-Chiang Chen, Yu-Sheng Chen