Patents by Inventor Hung Li

Hung Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11836358
    Abstract: A system comprises a power source and two power rails coupled to the power source. A storage device, comprising a non-volatile memory, a cache coupled to the non-volatile memory, and a control pin, is coupled to the second power rail. A power management controller is coupled to the first power rail and to a control pin of the storage device. The power management controller stops the provision of power via the first power rail and provides a signal to the storage device via the control pin when the provision of power via the first power rail is stopped. The storage device continues to receive power from the second power rail when the provision of power via the first power rail is stopped. The storage device stores data from the cache to the non-volatile memory in response to the receipt of the signal via the control pin.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: December 5, 2023
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Yu-Chen Cheng, Yu-Hung Li
  • Publication number: 20230387228
    Abstract: A semiconductor device a method of forming the same are provided. A semiconductor device includes a gate stack over a substrate. A first dielectric layer is over the gate stack. The first dielectric layer includes a first material. A second dielectric layer is over the first dielectric layer. The second dielectric layer includes a second material different from the first material. A first conductive feature is adjacent the gate stack. A second conductive feature is over and in physical contact with a topmost surface of the first conductive feature. A bottommost surface of the second conductive feature is in physical contact with a topmost surface of the second dielectric layer.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 30, 2023
    Inventors: Pei-Yu Chou, Jr-Hung Li, Tze-Liang Lee
  • Publication number: 20230387227
    Abstract: A first interconnect structure (e.g., a gate interconnect) of a butted contact (BCT) is etched and filled. The first interconnect structure is then etched back such that a portion of the first interconnect structure is removed, then a second interconnect structure and the remaining portion of the first interconnect structure are filled. In this way, the height of the remaining portion of the first interconnect structure that is to be filled is closer to the height of the second interconnect structure when the second interconnect structure is filled relative to fully filling the second interconnect structure and fully filling the first interconnect structure in a single deposition operation. This reduces the likelihood that filling the second interconnect structure will close the first interconnect structure before the first interconnect structure can be fully filled, which may otherwise result in the formation of a void in the first interconnect structure.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Te-Chih HSIUNG, I-Hung LI, Yi-Ruei JHAN, Yuan-Tien TU
  • Publication number: 20230389454
    Abstract: A method of forming a memory device includes the following operations. A first conductive plug is formed within a first dielectric layer over a substrate. A treating process is performed to transform a portion of the first conductive plug into a buffer layer, and the buffer layer caps the remaining portion of the first conductive plug. A phase change layer and a top electrode are sequentially formed over the buffer layer. A second dielectric layer is formed to encapsulate the top electrode and the underlying phase change layer. A second conductive plug is formed within the second dielectric layer and in physical contact with the top electrode. A filamentary bottom electrode is formed within the buffer layer.
    Type: Application
    Filed: August 2, 2023
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Jer-Fu Wang, Chao-Ching Cheng, Tzu-Chiang Chen
  • Publication number: 20230387235
    Abstract: A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.
    Type: Application
    Filed: August 6, 2023
    Publication date: November 30, 2023
    Inventors: Chao-Ching Cheng, Yi-Tse Hung, Hung-Li Chiang, Tzu-Chiang Chen, Lain-Jong Li, Jin Cai
  • Patent number: 11831086
    Abstract: An antenna structure includes a metal mechanism element, a ground element, a feeding radiation element, and a dielectric substrate. The metal mechanism element has a slot. The slot has a first closed end and a second closed end. The ground element is coupled to the metal mechanism element. The feeding radiation element has a feeding point. The feeding radiation element is coupled to the ground element. The dielectric substrate has a first surface and a second surface which are opposite to each other. The feeding radiation element is disposed on the first surface of the dielectric substrate. The second surface of the dielectric substrate is adjacent to the metal mechanism element. The slot of the metal mechanism element is excited to generate a first frequency band and a second frequency band. The feeding radiation element is excited to generate a third frequency band.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: November 28, 2023
    Assignee: WISTRON NEWEB CORP.
    Inventors: Po-Yen Chen, Kuan-Hung Li
  • Publication number: 20230378202
    Abstract: Disclosed herein, in some embodiments, is a memory device. The memory device includes a bottom electrode disposed over a substrate and a top electrode disposed over the bottom electrode. An upper surface of the bottom electrode faces away from the substrate. A bottom surface of the top electrode faces the substrate. A data storage layer is arranged between the bottom electrode and the top electrode. At least a portion of the bottom surface of the top electrode does not overlap with any portion of the top surface of the bottom electrode along a first direction parallel to the bottom surface of the top electrode. Furthermore, at least a portion of the top surface of the bottom electrode does not overlap with any portion of the bottom surface of the top electrode along the first direction.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 23, 2023
    Inventors: Hung-Li Chiang, Chao-Ching Cheng, Jung-Piao Chiu, Tzu-Chiang Chen, Yu-Sheng Chen
  • Publication number: 20230377984
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A Ge concentration in the first semiconductor layers is increased. A sacrificial gate structure is formed over the fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed. The second semiconductor layers in a channel region are removed, thereby releasing the first semiconductor layers in which the Ge concentration is increased. A gate structure is formed around the first semiconductor layers in which the Ge concentration is increased.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 23, 2023
    Inventors: Chao-Ching CHENG, I-Sheng CHEN, Hung-Li CHIANG, Tzu-Chiang CHEN
  • Publication number: 20230375920
    Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Application
    Filed: August 3, 2023
    Publication date: November 23, 2023
    Inventors: Ming-Hui WENG, Chen-Yu LIU, Chih-Cheng LIU, Yi-Chen KUO, Jia-Lin WEI, Yen-Yu CHEN, Jr-Hung LI, Yahru CHENG, Chi-Ming YANG, Tze-Liang LEE, Ching-Yu CHANG
  • Patent number: 11824088
    Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure further includes a first source/drain structure formed adjacent to the first nanostructures and a second source/drain structure formed adjacent to the second nanostructures. The semiconductor structure further includes a first contact plug formed over the first source/drain structure and a second contact plug formed over the second source/drain structure. In addition, a bottom portion of the first contact plug is lower than a bottom portion of the first nanostructures, and a bottom portion of the second contact plug is higher than a top portion of the second nanostructures.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Cheng, I-Sheng Chen, Tzu-Chiang Chen, Shih-Syuan Huang, Hung-Li Chiang
  • Patent number: 11822237
    Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, including combining a first precursor and a second precursor in a vapor state to form a photoresist material, and depositing the photoresist material over the substrate. A protective layer is formed over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation through the protective layer to form a latent pattern in the photoresist layer. The protective layer is removed, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: November 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Hui Weng, Chen-Yu Liu, Chih-Cheng Liu, Yi-Chen Kuo, Jia-Lin Wei, Yen-Yu Chen, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
  • Patent number: 11823957
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A Ge concentration in the first semiconductor layers is increased. A sacrificial gate structure is formed over the fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed. The second semiconductor layers in a channel region are removed, thereby releasing the first semiconductor layers in which the Ge concentration is increased. A gate structure is formed around the first semiconductor layers in which the Ge concentration is increased.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: November 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chao-Ching Cheng, I-Sheng Chen, Hung-Li Chiang, Tzu-Chiang Chen
  • Publication number: 20230369048
    Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Inventors: Jia-Lin WEI, Ming-Hui Weng, Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Yahru Cheng, Jr-Hung Li, Ching-Yu Chang, Tze-Liang Lee, Chi-Ming Yang
  • Publication number: 20230367208
    Abstract: An organometallic precursor for extreme ultraviolet (EUV) lithography is provided. An organometallic precursor includes an aromatic di-dentate ligand, a transition metal coordinated to the aromatic di-dentate ligand, and an extreme ultraviolet (EUV) cleavable ligand coordinated to the transition metal. The aromatic di-dentate ligand includes a plurality of pyrazine molecules.
    Type: Application
    Filed: July 20, 2023
    Publication date: November 16, 2023
    Inventors: Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Jr-Hung Li, Chi-Ming Yang, Tze-Liang Lee
  • Publication number: 20230361217
    Abstract: A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion.
    Type: Application
    Filed: July 13, 2023
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Cheng, Chun-Chieh Lu, Hung-Li Chiang, Tzu-Chiang Chen
  • Publication number: 20230361177
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a heat transfer layer disposed over a substrate, a channel material layer, a gate structure and source and drain terminals. The channel material layer has a first surface and a second surface opposite to the first surface, and the channel material layer is disposed on the heat transfer layer with the first surface in contact with the heat transfer layer. The gate structure is disposed above the channel material layer. The source and drain terminals are in contact with the channel material layer and located at two opposite sides of the gate structure.
    Type: Application
    Filed: July 14, 2023
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tse Hung, Ang-Sheng Chou, Hung-Li Chiang, Tzu-Chiang Chen, Chao-Ching Cheng
  • Patent number: 11804067
    Abstract: A fingerprint sensing device and a wearable electronic device are provided. The fingerprint sensing device includes an image sensor and a processor. The image sensor is arranged below a fingerprint sensing area. The processor is coupled to the image sensor. The processor senses a finger placed above the fingerprint sensing area through the image sensor during a fingerprint sensing period to obtain a first fingerprint image. The processor continuously senses the finger placed above the fingerprint sensing area through the image sensor during a physiological information sensing period, so as to obtain a physiological characteristic signal.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: October 31, 2023
    Assignee: Guangzhou Tyrafos Semiconductor Technologies Co., LTD
    Inventors: Ping-Hung Yin, Chih-Hung Li, Haici Kong, Sueishuang Liou
  • Patent number: 11805662
    Abstract: A memory device includes a first electrode, a selector layer and a plurality of first work function layers. The first work function layers are disposed between the first electrode and the selector layer, and a work function of the first work function layer increases as the first work function layer becomes closer to the selector layer.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: October 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Jung-Piao Chiu, Tzu-Chiang Chen, Yu-Sheng Chen, Xinyu Bao
  • Publication number: 20230343134
    Abstract: A fingerprint sensing device and a wearable electronic device are provided. The fingerprint sensing device includes an image sensor and a processor. The image sensor is arranged below a fingerprint sensing area. The processor is coupled to the image sensor. The processor senses a finger placed above the fingerprint sensing area through the image sensor during a fingerprint sensing period to obtain a first fingerprint image. The processor continuously senses the finger placed above the fingerprint sensing area through the image sensor during a physiological information sensing period, so as to obtain a physiological characteristic signal.
    Type: Application
    Filed: October 12, 2022
    Publication date: October 26, 2023
    Applicant: Guangzhou Tyrafos Semiconductor Technologies Co., LTD
    Inventors: Ping-Hung Yin, Chih-Hung Li, Haici KONG, Sueishuang LIOU
  • Publication number: 20230343842
    Abstract: A method may include forming a first silicon nitride layer in an opening of the semiconductor device and on a top surface of the semiconductor device, wherein the semiconductor device includes an epitaxial source/drain and a metal gate. The method may include forming a second silicon nitride layer on the first silicon nitride layer, as a sacrificial layer, and removing the second silicon nitride layer from sidewalls of the first silicon nitride layer formed in the opening. The method may include removing the second silicon nitride layer and the first silicon nitride layer formed at a bottom of the opening, and depositing a metal layer in the opening to form a metal drain in the opening of the semiconductor device.
    Type: Application
    Filed: June 27, 2023
    Publication date: October 26, 2023
    Inventors: Tzu-Yang HO, Tsai-Jung HO, Jr-Hung LI, Tze-Liang LEE