Patents by Inventor Hung Li

Hung Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11798989
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Publication number: 20230335638
    Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.
    Type: Application
    Filed: April 27, 2023
    Publication date: October 19, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tsung-Yu Yang, Shin-Hung Li, Nien-Chung Li, Chang-Po Hsiung
  • Publication number: 20230335637
    Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.
    Type: Application
    Filed: April 27, 2023
    Publication date: October 19, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tsung-Yu Yang, Shin-Hung Li, Nien-Chung LI, Chang-Po Hsiung
  • Publication number: 20230326754
    Abstract: A method of forming a pattern in a photoresist layer includes forming a photoresist layer over a substrate, and reducing moisture or oxygen absorption characteristics of the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Application
    Filed: May 31, 2023
    Publication date: October 12, 2023
    Inventors: Yi-Chen KUO, Chih-Cheng Liu, Ming-Hui Weng, Jia-Lin Wei, Yen-Yu Chen, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
  • Publication number: 20230327020
    Abstract: An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 12, 2023
    Inventors: Hung-Li Chiang, Chih-Sheng Chang, Tzu-Chiang Chen
  • Publication number: 20230326518
    Abstract: A memory device and an operation method thereof are provided. The memory device includes memory cells, each having a static random access memory (SRAM) cell and a non-volatile memory cell. The SRAM cell is configured to store complementary data at first and second storage nodes. The non-volatile memory cell is configured to replicate and retain the complementary data before the SRAM cell loses power supply, and to rewrite the replicated data to the first and second storage nodes of the SRAM cell after the power supply of the SRAM cell is restored.
    Type: Application
    Filed: April 8, 2022
    Publication date: October 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jer-Fu Wang, Hung-Li Chiang, Yi-Tse Hung, Tzu-Chiang Chen, Meng-Fan Chang
  • Publication number: 20230327137
    Abstract: The present invention provides a manufacturing method of an electrode. The method includes steps of: mixing a first catalyst with a first average particle size, a second catalyst with a second average particle size, a first conductive agent, a first adhesive, and a solvent to form a first mixture, wherein a weight ratio of the first catalyst to the second catalyst is 5:1 to 1:5; stirring the first mixture to obtain a second mixture; rolling the second mixture into a catalytic layer; and pressing the catalytic layer with a conductive current collector and a gas diffusion film to obtain the electrode.
    Type: Application
    Filed: October 26, 2022
    Publication date: October 12, 2023
    Inventors: Kuang-Che Lee, Chia-Hung Li, Chien-Yao Huang, Chiun-Shian Tsai, Ting-Chuan Lee, Chiun- Rung Tsai
  • Patent number: 11784046
    Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Lin Wei, Ming-Hui Weng, Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Yahru Cheng, Jr-Hung Li, Ching-Yu Chang, Tze-Liang Lee, Chi-Ming Yang
  • Publication number: 20230317469
    Abstract: A method of forming a semiconductor device includes forming a source/drain region over a substrate; forming a first interlayer dielectric over the source/drain region; forming a gate structure over the substrate and laterally adjacent to the source/drain region; and forming a gate mask over the gate structure, the forming the gate mask comprising: etching a portion of the gate structure to form a recess relative to a top surface of the first interlayer dielectric; depositing a first dielectric layer over the gate structure in the recess and over the first interlayer dielectric; etching a portion of the first dielectric layer; depositing a semiconductor layer over the first dielectric layer in the recess; and planarizing the semiconductor layer to be coplanar with the first interlayer dielectric. In another embodiment, the method further includes forming a gate spacer over the substrate, wherein the etching the portion of the gate structure further comprises etching a portion of the gate spacer.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 5, 2023
    Inventors: Bor Chiuan Hsieh, Po-Hsien Cheng, Tsai-Jung Ho, Po-Cheng Shih, Jr-Hung Li, Tze-Liang Lee
  • Patent number: 11773506
    Abstract: An IC fabrication system for facilitating improved thermal uniformity includes a chamber within which an IC process is performed on a substrate, a heating mechanism configured to heat the substrate, and a substrate-retaining device configured to retain the substrate in the chamber. The substrate-retaining device includes a contact surface configured to contact an edge of the retained substrate without the substrate-retaining device contacting a circumferential surface of the retained substrate. The substrate-retaining device includes a plurality of contact regions and a plurality of noncontact regions disposed at a perimeter, where the plurality of noncontact regions is interspersed with the plurality of contact regions. Each of the plurality of noncontact regions includes the contact surface.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hung Lin, Jr-Hung Li, Chang-Shen Lu, Tze-Liang Lee, Chii-Horng Li
  • Publication number: 20230309285
    Abstract: A static random-access memory (SRAM) cell including a transistor is introduced. The transistor includes substrate and gate stack structure disposed over the substrate, in which the gate stack structure includes a gate oxide layer, a ferroelectric layer, and a conductive layer. The gate oxide layer is disposed over the substrate; the ferroelectric layer is disposed over the gate oxide layer, wherein the ferroelectric layer has a negative capacitance effect; and the first conductive layer, disposed over the ferroelectric layer. A method of adjusting a threshold voltage of a transistor in the SRAM is also introduced.
    Type: Application
    Filed: March 24, 2022
    Publication date: September 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang
  • Publication number: 20230298651
    Abstract: A data processing method, a data processing circuit, and a computing apparatus are provided. In the method, data is obtained. A first value of a bit of the data is switched into a. second value according to data distribution and an accessing property of memory. The second value of the bit is stored in the memory in response to switching the bit.
    Type: Application
    Filed: March 18, 2022
    Publication date: September 21, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang
  • Patent number: 11764431
    Abstract: Battery packs according to some embodiments of the present technology may include a longitudinal beam. The packs may include a plurality of battery cells disposed adjacent the longitudinal beam. Each battery cell may be characterized by a first surface, and a second surface opposite the first surface. Each battery cell may be characterized by a third surface extending vertically between the first surface and the second surface. The first surface may face the longitudinal beam, and battery terminals may extend from the third surface. Each battery cell may be characterized by a fourth surface opposite the third surface. The packs may include a lid coupled with the first surface of each battery cell of the plurality of battery cells. The packs may include a base coupled with the second surface of each battery cell of the plurality of battery cells.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: September 19, 2023
    Assignee: Apple Inc.
    Inventors: Nivay Anandarajah, Evan D. Maley, Alexander J. Clarabut, Yu-Hung Li, John M. Schoech
  • Patent number: 11759799
    Abstract: A shower head includes a housing, and a jet faceplate mounted to the housing and including a first water jetting area composed of a plurality of subunits and a second water jetting area having a second jet hole therein. The subunits are arranged to present an arc-shaped distribution, each defining therein a plurality of first jet holes. The subunits are in a fan-shaped area of the jet faceplate so that the water line of the ejected water can be concentrated and fan-shaped, enhancing the effect of removing dirt.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: September 19, 2023
    Assignee: GLOBE UNION INDUSTRIAL CORP.
    Inventors: Chun-Hung Li, Hui-Ling Chiu, Tun-Yao Tsai
  • Patent number: 11757045
    Abstract: A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Cheng, Chun-Chieh Lu, Hung-Li Chiang, Tzu-Chiang Chen
  • Publication number: 20230282750
    Abstract: Methods of forming improved dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a transistor structure on a semiconductor substrate; a first dielectric layer on the transistor structure; a second dielectric layer on the first dielectric layer, the second dielectric layer having a nitrogen concentration greater than a nitrogen concentration of the first dielectric layer; a first conductive structure extending through the second dielectric layer and the first dielectric layer, the first conductive structure being electrically coupled to a first source/drain region of the transistor structure, a top surface of the first conductive structure being level with a top surface of the second dielectric layer; and a second conductive structure physically and electrically coupled to the first conductive structure, a bottom surface of the second conductive structure being a first distance below the top surface of the second dielectric layer.
    Type: Application
    Filed: June 15, 2022
    Publication date: September 7, 2023
    Inventors: Yu-Lien Huang, Tze-Liang Lee, Jr-Hung Li, Chi-Hao Chang, Hao-Yu Chang, Pei-Yu Chou
  • Patent number: 11744542
    Abstract: A method for evaluating a movement state of a heart is provided and includes: obtaining a plurality of consecutive heart ultrasound images corresponding to a heart and accordingly estimating a plurality of left ventricular volumes corresponding to the heart ultrasound images; finding a plurality of specific extremums in the left ventricular volumes and accordingly estimating a plurality of time differences among the specific extremums; estimating a statistical characteristic value of the time differences based on the time differences; and determining that an abnormal movement state of the heart occurs in response to determining that at least one of the time differences deviates from the statistical characteristic value up to a predetermined threshold.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: September 5, 2023
    Assignee: Acer Incorporated
    Inventors: Hung-Sheng Hsu, Chien-Hung Li, Yi-Jin Huang
  • Patent number: 11749718
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a heat transfer layer disposed over a substrate, a channel material layer, a gate structure and source and drain terminals. The channel material layer has a first surface and a second surface opposite to the first surface, and the channel material layer is disposed on the heat transfer layer with the first surface in contact with the heat transfer layer. The gate structure is disposed above the channel material layer. The source and drain terminals are in contact with the channel material layer and located at two opposite sides of the gate structure.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tse Hung, Ang-Sheng Chou, Hung-Li Chiang, Tzu-Chiang Chen, Chao-Ching Cheng
  • Patent number: 11742399
    Abstract: A method may include forming a first silicon nitride layer in an opening of the semiconductor device and on a top surface of the semiconductor device, wherein the semiconductor device includes an epitaxial source/drain and a metal gate. The method may include forming a second silicon nitride layer on the first silicon nitride layer, as a sacrificial layer, and removing the second silicon nitride layer from sidewalls of the first silicon nitride layer formed in the opening. The method may include removing the second silicon nitride layer and the first silicon nitride layer formed at a bottom of the opening, and depositing a metal layer in the opening to form a metal drain in the opening of the semiconductor device.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: August 29, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yang Ho, Tsai-Jung Ho, Jr-Hung Li, Tze-Liang Lee
  • Patent number: D998763
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: September 12, 2023
    Assignee: GLOBE UNION INDUSTRIAL CORP.
    Inventors: Yi Ping Lin, Chun Hung Li