Patents by Inventor Hung Li

Hung Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11742352
    Abstract: A semiconductor device includes first and second source/drain structures, a channel layer, a gate structure, and an epitaxial layer. The channel layer is above the first source/drain structure. The second source/drain structure is above the channel layer. The gate structure is on a first side surface of the channel layer. The epitaxial layer forms a P-N junction with a second side surface of the channel layer.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Li Chiang, Szu-Wei Huang, Chih-Chieh Yeh, Yee-Chia Yeo
  • Patent number: 11735259
    Abstract: A read method and a write method for a memory circuit are provided, wherein the memory circuit includes a memory cell and a selector electrically coupled to the memory cell. The read method includes applying a first voltage to the selector, wherein a first voltage level of the first voltage is larger than a voltage threshold corresponding to the selector; and applying, after the applying of the first voltage, a second voltage to the selector to sense one or more bit values stored in the memory cell, wherein a second voltage level of the second voltage is constant and smaller than the voltage threshold, wherein a first duration of the applying of the first voltage is smaller than a second duration of the applying of the second voltage, wherein the second voltage is applied following the end of the first duration.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: August 22, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Carlos H. Diaz, Hung-Li Chiang, Tzu-Chiang Chen, Yih Wang
  • Publication number: 20230260832
    Abstract: Semiconductor devices and methods of manufacture are presented herein in which a etch stop layer is selectively deposited over a conductive contact. A dielectric layer is formed over the etch stop layer and an opening is formed through the dielectric layer and the etch stop layer to expose the conductive contact. Conductive material is then deposited to fill the opening.
    Type: Application
    Filed: June 3, 2022
    Publication date: August 17, 2023
    Inventors: Yu-Kai Lin, Po-Cheng Shih, Jr-Hung Li, Tze-Liang Lee
  • Publication number: 20230263078
    Abstract: The disclosure provides a memory device, a method for configuring a first memory cell in an N-bit memory unit of a memory array, and a memory array. The memory device includes a memory array including an N-bit memory unit, wherein N is a positive integer. The N-bit memory unit includes a first memory cell, used to characterize at least two first bits of a plurality of least significant bits of the N-bit memory unit.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang
  • Patent number: 11725278
    Abstract: A system and method for plasma enhanced deposition processes. An exemplary semiconductor manufacturing system includes a susceptor configured to hold a semiconductor wafer and a sector disposed above the susceptor. The sector includes a first plate and an overlying second plate, operable to form a plasma there between. The first plate includes a plurality of holes extending through the first plate, which vary in at least one of diameter and density from a first region of the first plate to a second region of the first plate.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kun-Mo Lin, Yi-Hung Lin, Jr-Hung Li, Tze-Liang Lee, Ting-Gang Chen, Chung-Ting Ko
  • Patent number: 11726405
    Abstract: An organometallic precursor for extreme ultraviolet (EUV) lithography is provided. An organometallic precursor includes an aromatic di-dentate ligand, a transition metal coordinated to the aromatic di-dentate ligand, and an extreme ultraviolet (EUV) cleavable ligand coordinated to the transition metal. The aromatic di-dentate ligand includes a plurality of pyrazine molecules.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Jr-Hung Li, Chi-Ming Yang, Tze-Liang Lee
  • Publication number: 20230253496
    Abstract: A semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor and a second transistor. The substrate includes a high-voltage region and a low-voltage region. The first transistor is disposed on the HV region, and includes a first gate dielectric layer disposed on a first base, and a first gate electrode on the first gate dielectric layer. The first gate dielectric layer includes a composite structure having a first dielectric layer and a second dielectric layer stacked sequentially. The second transistor is disposed on the LV region, and includes a fin shaped structure protruded from a second base on the substrate, and a second gate electrode disposed on the fin shaped structure. The first dielectric layer covers sidewalls of the second gate electrode and a top surface of the first dielectric layer is even with a top surface of the second gate electrode.
    Type: Application
    Filed: March 7, 2022
    Publication date: August 10, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Shin-Hung Li
  • Patent number: 11719880
    Abstract: A perovskite optical element includes a light guiding unit and a luminescent layer. The light guiding unit is configured to conduct light and serves as a resonant cavity. The luminescent layer is a thin film made of perovskite material and clads the light guiding unit. The luminescent layer is configured to be excited by an excitation module to emit light. The light is conducted and output by the light guiding unit. A manufacturing method of a perovskite optical element includes preparing a dip coating solution; dipping a single crystal optical fiber in the dip coating solution for one hour, removing the single crystal optical fiber out of the dip coating solution, and drying the single crystal optical fiber; and placing the single crystal optical fiber into a tube furnace, heating the crystal optical fiber, and introducing synthetic molecules into the tube furnace.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: August 8, 2023
    Assignee: NATIONAL DONG HWA UNIVERSITY
    Inventors: Duc-Huy Nguyen, Jia-Yuan Sun, Chia-Yao Lo, Jia-Ming Liu, Wan-Shao Tsai, Ming-Hung Li, Sin-Jhang Yang, Cheng-Chia Lin, Shien-Der Tzeng, Yuan-Ron Ma, Ming-Yi Lin, Chien-Chih Lai
  • Patent number: 11721376
    Abstract: A memory device and a memory circuit is provided. The memory device includes a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ), a read word line, a selector and a write word line. The MTJ stands on the SOT layer. The read word line is electrically connected to the MTJ. The write word line is connected to the SOT layer through the selector. The write word line is electrically connected to the SOT layer when the selector is turned on, and the write word line is electrically isolated from the SOT layer when the selector is in an off state.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: August 8, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Chung-Te Lin, Shy-Jay Lin, Tzu-Chiang Chen, Ming-Yuan Song, Hon-Sum Philip Wong
  • Patent number: 11715798
    Abstract: An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: August 1, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Chih-Sheng Chang, Tzu-Chiang Chen
  • Publication number: 20230240078
    Abstract: A memory device including a plurality of memory cells, at least one of the plurality of memory cells includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first drain/source path and a first gate structure electrically coupled to a write word line. The second transistor includes a second drain/source path and a second gate structure electrically coupled to the first drain/source path of the first transistor. The third transistor includes a third drain/source path electrically coupled to the second drain/source path of the second transistor and a third gate structure electrically coupled to a read word line. Where, the first transistor, and/or the second transistor, and/or the third transistor is a ferroelectric field effect transistor or a negative capacitance field effect transistor.
    Type: Application
    Filed: May 27, 2022
    Publication date: July 27, 2023
    Inventors: Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang
  • Publication number: 20230231033
    Abstract: The invention provides a manufacturing method of a semiconductor structure, the method includes providing a substrate, forming two shallow trench isolation structures in the substrate. A first region, a second region and a third region are defined between the two shallow trench isolation structures, and the second region is located between the first region and the third region. Next, an oxide layer is formed in the first region, the second region and the third region, and the oxide layer directly contacts the two shallow trench isolation structures. The oxide layer in the second region is then removed, and another oxide layer is formed in the first region, the second region and the third region, so that a thick oxide layer is formed in the first and third regions, and a thin oxide layer is formed in the second region.
    Type: Application
    Filed: March 23, 2023
    Publication date: July 20, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Shin-Hung Li
  • Patent number: 11705332
    Abstract: A method of forming a pattern in a photoresist layer includes forming a photoresist layer over a substrate, and reducing moisture or oxygen absorption characteristics of the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: July 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen Kuo, Chih-Cheng Liu, Ming-Hui Weng, Jia-Lin Wei, Yen-Yu Chen, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
  • Publication number: 20230225132
    Abstract: A memory structure includes a substrate. The memory structure further includes a first transistor, wherein the first transistor is a first distance from the substrate. The memory structure further includes a second transistor, wherein the second transistor is a second distance from the substrate, and the first distance is different from the second distance, and a first source/drain (S/D) region of the first transistor is connected to a second S/D region of the second transistor. The memory structure further includes a plurality of storage elements electrically connected to both the first transistor and the second transistor, wherein each of the plurality of storage elements is a third distance from the substrate, and the third distance is different from both the first distance and the second distance.
    Type: Application
    Filed: April 22, 2022
    Publication date: July 13, 2023
    Inventors: Hung-Li CHIANG, Jer-Fu WANG, Yi-Tse HUNG, Tzu-Chiang CHEN, Meng-Fan CHANG, Hon-Sum Philip WONG
  • Publication number: 20230225218
    Abstract: A memory device includes a transistor and a memory cell. The transistor includes a gate electrode disposed over a substrate and source/drain regions in the substrate beside the gate electrode. The memory cell is disposed over the transistor and includes a bottom electrode electrically connected to one of the source/drain regions, a top electrode disposed over the bottom electrode, and a first bit and a second bit separated from each other and disposed between the bottom electrode and the top electrode.
    Type: Application
    Filed: January 13, 2022
    Publication date: July 13, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang
  • Patent number: 11699209
    Abstract: There is provided a method for embedding a digital watermark into and extracting a digital watermark from a numerical data set. In accordance with embodiments of the present disclosure, there is provided a method for embedding a digital watermark into a numerical data set. The method includes selecting portions of the numerical data set identified as data noise, the selected portions to be used for embedding the digital watermark into the numerical data set, the digital watermark being unique for each recipient of the numerical data. The method further includes replacing the least significant bit (LSB) of at least some of the selected portions of the numerical data set with at least portion of the digital watermark.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: July 11, 2023
    Assignee: HUAWEI CLOUD COMPUTING TECHNOLOGIES CO., LTD.
    Inventors: Roozbeh Jalali, Haolin Guo, Michael Chih Hung Li, Zanqing Zhang
  • Publication number: 20230213697
    Abstract: A backlight module includes a light guide plate, a light source, multiple first optical microstructures, and multiple second optical microstructures. The first optical microstructures and the second optical microstructures are disposed on the bottom surface of the light guide plate. Each of the first optical microstructures has a first light receiving surface facing the light source. Each of the second optical microstructures has a second light receiving surface facing the light source. A first angle is included between the first light receiving surface and the bottom surface. A second angle is included between the second light receiving surface and the bottom surface. The second angle is different from the first angle. A display apparatus adopting the backlight module is also provided.
    Type: Application
    Filed: December 20, 2022
    Publication date: July 6, 2023
    Applicant: Coretronic Corporation
    Inventors: Tzeng-Ke Shiau, Hsuan Chou, Hung-Li Pan, Yi-Cheng Lin, Chia-Liang Kang, Shih-Wei Liu, Wei-Chun Yang, Cheng-Yi Tseng
  • Publication number: 20230215914
    Abstract: A semiconductor high-voltage device includes a semiconductor substrate; a high-voltage well in the semiconductor substrate; a drift region in the high-voltage well; a recessed channel region adjacent to the drift region; a heavily doped drain region in the drift region and spaced apart from the recessed channel; an isolation structure between the recessed channel region and the heavily doped drain region in the drift region; a buried gate dielectric layer on the recessed channel region, wherein the top surface of the buried gate dielectric layer is lower than the top surface of the heavily doped drain region; and a gate on the buried gate dielectric layer.
    Type: Application
    Filed: January 18, 2022
    Publication date: July 6, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Shin-Hung Li
  • Publication number: 20230206446
    Abstract: An image processing apparatus for evaluating cardiac images and a ventricular status identification method are provided. In the method, a region of interest (ROI) is determined from multiple target images, a variation in grayscale values of multiple pixels in the ROIs of each target image is determined, and one or more representative images are obtained according to the variation in the grayscale values. The target image is related to the pixels within an endocardial contour of a left ventricle. A boundary of the ROI is approximately located at two sides of a bottom of the endocardial contour. The ROI corresponds to a mitral valve. The variation in the grayscale values is related to a motion of the mitral valve. The representative image is for evaluating a status of the left ventricle.
    Type: Application
    Filed: February 21, 2023
    Publication date: June 29, 2023
    Applicant: Acer Incorporated
    Inventors: Hung-Sheng Hsu, Chien-Hung Li, Yi-Jin Huang
  • Publication number: 20230197843
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first drift region, a first source/drain region, and a gate oxide layer. The gate structure and the gate oxide layer are disposed on the semiconductor substrate. The first drift region is disposed in the semiconductor substrate. The first source/drain region is disposed in the first drift region. At least a part of a first portion of the gate oxide layer is disposed between the gate structure and the semiconductor substrate in a vertical direction. A second portion of the gate oxide layer is disposed between the first portion and the first source/drain region in a horizontal direction. The second portion includes a bottom extending downwards and a first concave top surface located above the bottom. A part of the first drift region is located under the first portion and the second portion of the gate oxide layer.
    Type: Application
    Filed: January 18, 2022
    Publication date: June 22, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tsung-Yu Yang, Shin-Hung Li, Ruei-Jhe Tsao, Che-Hua Chang