Abstract: The present subject matter relates to self-healing keyboards. In an example implementation, a self-healing keyboard of an electronic device comprises a self-healing film having a self-healing layer disposed over a keyboard. The self-healing layer is composed of polyurethane, epoxy vinyl ester, epoxy, polyurethane microcapsules filled with silane compound, and a polysiloxane mixture.

Abstract: In one example, touchpad assembly is disclosed, which may include a bottom cover, a horizontal elastic member flexibly positioned on the bottom cover, a balancing bar disposed on the bottom cover and substantially parallel to the horizontal elastic member, and a metal dome. The metal dome may include a first end fixedly connected to the bottom cover via a first fixture, and a second end to hold the horizontal elastic member and the balancing bar such that the balancing bar is flexibly engaged with the bottom cover. The balancing bar, the metal dome, and the horizontal elastic member may control a flexure of a touchpad when the touchpad is pressed.

Abstract: A fixation device performing a fixation process on a medium in conjunction with a pressure roller includes: a fuser heating to a predetermined temperature to perform the fixation process; a temperature sensor senses a temperature of the fuser as time elapses; a controller electrically connected to the fuser and the temperature sensor; and a database connected to the controller and storing heating time data; wherein the controller obtains a heating time period, during which a temperature of the fuser rises from a non-environment temperature to the predetermined temperature, through the temperature sensor, and judges whether the heating time period falls within a qualified range specified by the heating time data. If the heating time period does not fall within the qualified range, then the controller provides an abnormal message, so that the problem of the fixation device can be solved.

Abstract: A production line automatically allocating device includes a processor and a storage, wherein the processor is electrically connected to the storage. The storage stores a plurality of first fabrication process data, a plurality of machine function data and a plurality of machine status feedback data. The processor establishes a plurality of machine function group data according to the plurality of machine function data, determines first production line allocation data according to the plurality of machine function group data and the plurality of first fabrication process data, and updates the first production line allocation data according to the plurality of machine status feedback data in real time.

Abstract: A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.

Abstract: The fin structure includes a first portion and a second, lower portion separated at a transition. The first portion has sidewalls that are substantially perpendicular to the major surface of the substrate. The lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width.

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Abstract: A computer implemented method for routing preservation is presented. The method includes decomposing, using the computer, a geometric relationship between a first module, a second module, and a routing path of a source layout, when the computer is invoked to route the solution path. The method further includes disposing, using the computer, the routing path in a solution layout in accordance with the geometric relationship. The solution layout is not defined by a scaling of the source layout.

Abstract: An exemplary method of forming a fin field effect transistor that includes first and second etching processes to form a fin structure. The fin structure includes an upper portion and a lower portion separated at a transition. The upper portion has sidewalls that are substantially perpendicular to the major surface of the substrate. The lower portion has tapered sidewalls on opposite sides of the upper portion and a base having a second width larger than the first width.

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Abstract: A method for monitoring gas in a wafer processing system is provided. The method includes producing an exhaust flow in an exhausting conduit from a processing chamber. The method further includes placing a gas sensor in fluid communication with a detection point located in the exhausting conduit via a sampling tube that passes through a through hole formed on the exhausting conduit. The detection point is located away from the through hole. The method also includes detecting a gas condition at the detection point with the gas sensor. In addition, the method also includes analyzing the gas condition detected by the gas sensor to determine if the gas condition in the exhausting conduit is in a range of values.

Abstract: An equipment maintenance prediction system and an operation method for the equipment maintenance prediction system are provided. The operation method includes steps of: configuring the processor to configure the factor decision module to select one of a plurality of parameter types as a decision parameter type according to a key parameter type, wherein the decision parameter type and the key parameter type are most correlative; configuring the processor to configure the prediction module to generate a prediction model according to a part of a plurality of historical sensing values of the decision parameter type and formulate a maintenance alerting condition according to a part of a plurality of historical sensing values of the key parameter type; and configuring the processor to configure the maintenance alerting module to monitor and alert according to the maintenance alerting condition.

Abstract: The present subject matter relates to backlight keyboards. In an example implementation of the present subject matter, backlight keyboards and methods of fabricating lighting units for such backlight keyboards are described. In an example, a backlight keyboard includes a substrate and a plurality of Light Emitting Diodes (LEDs) disposed on the substrate. The backlight keyboard further includes a printed circuit disposed on the substrate, where the printed circuit comprises of a plurality of electrical connections to provide electric current to the plurality of LEDs, and where width of each of the plurality of electrical connections is predefined to control brightness of a corresponding LED from amongst the plurality of LEDs.

Abstract: In one example, a metal-plastic composite structure for an electronic device is described, which includes a micro-arc oxidized metal substrate and at least one plastic film disposed on the micro-arc oxidized metal substrate using a superplastic forming process.

Abstract: The present subject matter relates to self-healing touch-surface components. In an example implementation, a self-healing touch-surface component of an electronic device comprises a self-healing layer disposed over a touch-surface component. The self-healing layer includes polyurethane, polyester, epoxy, polyurethane microcapsules filled with di-n-butyltin dilaurate, and a polysiloxane mixture.

Abstract: A semiconductor device includes a substrate, a carbon-containing diffusion barrier, a phosphorus-containing source/drain feature, a gate structure, and a gate spacer. The substrate has a channel region. The carbon-containing diffusion barrier is present in the substrate. The phosphorus-containing source/drain feature is present in the substrate, and the carbon-containing diffusion barrier is between the channel region and the phosphorus-containing source/drain feature. The gate is present over the channel region of the substrate. The gate spacer abuts the gate structure and is present over a portion of the phosphorus-containing source/drain feature.

Abstract: A layout-generation method for an IC is provided. The layout-generation method includes accessing data of a schematic design of the IC; generating a hypergraph from the schematic design; transforming a plurality of constraints into a plurality of weighted edges in the hypergraph; continuing partitioning the hypergraph by the weighted edges until a plurality of multilevel groups are obtained to generate a layout; and verifying the layout to fabricate the IC.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.

Abstract: A semiconductor structure includes a semiconductor substrate comprising a PMOS region and an NMOS region; a PMOS device in the PMOS region; and an NMOS device in the NMOS region. The PMOS device includes a first gate stack on the semiconductor substrate; a first offset spacer on a sidewall of the first gate stack; a stressor in the semiconductor substrate and adjacent to the first offset spacer; and a first raised source/drain extension region on the stressor and adjoining the first offset spacer, wherein the first raised source/drain extension region has a higher p-type dopant concentration than the stressor.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. An upper portion of the fin structure includes a first surface and a second surface which is inclined to the first surface. The semiconductor device structure also includes an isolation feature surrounding a lower portion of the fin structure. The semiconductor device structure further includes a passivation layer covering the first surface and the second surface of the upper portion. The passivation layer includes a semiconductor material and has a substantially uniform thickness. In addition, the semiconductor device structure includes an interfacial layer over the passivation layer. The interfacial layer includes the semiconductor material. The interfacial layer has a first portion covering the fin structure and a second portion covering the isolation feature.