Patents by Inventor Hung Q. Le

Hung Q. Le has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190286446
    Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.
    Type: Application
    Filed: June 6, 2019
    Publication date: September 19, 2019
    Inventors: SUNDEEP CHADHA, ROBERT A. CORDES, DAVID A. HRUSECKY, HUNG Q. LE, JENTJE LEENSTRA, DUNG Q. NGUYEN, BRIAN W. THOMPTO, ALBERT J. VAN NORSTRAND, Jr.
  • Patent number: 10409598
    Abstract: Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: September 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen, Brian W. Thompto, Albert J. Van Norstrand, Jr.
  • Publication number: 20190265978
    Abstract: Managing an issue queue for fused instructions and paired instructions in a microprocessor including dispatching a fused instruction to a first entry in a double issue queue; dispatching two paired instructions to a second entry in the double issue queue; issuing the fused instruction during a single cycle to an execution unit in response to determining, by the issue queue logic, that the fused instruction is ready to issue; and issuing, by the issue queue logic, the first instruction of the two paired instructions to the execution unit in response to determining, by the issue queue logic, that the first instruction of the two paired instructions is ready to issue.
    Type: Application
    Filed: May 9, 2019
    Publication date: August 29, 2019
    Inventors: MICHAEL J. GENDEN, HUNG Q. LE, DUNG Q. NGUYEN, BRIAN W. THOMPTO
  • Publication number: 20190265979
    Abstract: Managing an issue queue for fused instructions and paired instructions in a microprocessor including dispatching a fused instruction to a first entry in a double issue queue; dispatching two paired instructions to a second entry in the double issue queue; issuing the fused instruction during a single cycle to an execution unit in response to determining, by the issue queue logic, that the fused instruction is ready to issue; and issuing, by the issue queue logic, the first instruction of the two paired instructions to the execution unit in response to determining, by the issue queue logic, that the first instruction of the two paired instructions is ready to issue.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Inventors: MICHAEL J. GENDEN, HUNG Q. LE, DUNG Q. NGUYEN, BRIAN W. THOMPTO
  • Patent number: 10394565
    Abstract: Managing an issue queue for fused instructions and paired instructions in a microprocessor including dispatching a fused instruction to a first entry in a double issue queue; dispatching two paired instructions to a second entry in the double issue queue; issuing the fused instruction during a single cycle to an execution unit in response to determining, by the issue queue logic, that the fused instruction is ready to issue; and issuing, by the issue queue logic, the first instruction of the two paired instructions to the execution unit in response to determining, by the issue queue logic, that the first instruction of the two paired instructions is ready to issue.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Genden, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto
  • Patent number: 10387147
    Abstract: Managing an issue queue for fused instructions and paired instructions in a microprocessor including dispatching a fused instruction to a first entry in a double issue queue; dispatching two paired instructions to a second entry in the double issue queue; issuing the fused instruction during a single cycle to an execution unit in response to determining, by the issue queue logic, that the fused instruction is ready to issue; and issuing, by the issue queue logic, the first instruction of the two paired instructions to the execution unit in response to determining, by the issue queue logic, that the first instruction of the two paired instructions is ready to issue.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Genden, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto
  • Publication number: 20190250918
    Abstract: A system and process for managing thread execution includes providing two data register sets coupled to a processor and using, by the processor, the two register sets as first-level registers for thread execution. A portion of main memory or cache memory is assigned as second-level registers where the second-level registers serve as registers of at least one of the two data register sets for executing the threads. Data for the threads may be moved between the first-level registers and second-level registers for different modes of thread processing.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Inventors: Christopher M. Abernathy, Mary D. Brown, Susan E. Eisen, James A. Kahle, Hung Q. Le, Dung Q. Nguyen
  • Patent number: 10296339
    Abstract: A system and process for managing thread transitions includes providing two data register sets coupled to a processor and using, by the processor, the two register sets as first-level registers for thread execution. A determination is made whether a quantity of the first-level registers needed to execute one or more threads exceeds a quantity of the first-level registers of the two data register sets. Responsive to determining that the quantity of the first-level registers needed to execute the one or more threads exceeds the quantity of the first-level registers of the two data register sets, a portion of main memory or cache memory is assigned as second-level registers where the second-level registers serve as registers of at least one of the two data register sets for executing the one or more threads.
    Type: Grant
    Filed: August 11, 2018
    Date of Patent: May 21, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher M. Abernathy, Mary D. Brown, Susan E. Eisen, James A. Kahle, Hung Q. Le, Dung Q. Nguyen
  • Patent number: 10289415
    Abstract: Method and system for restoring results to a register file of a processing unit is provided. An instruction is dispatched in a processing slice of the processing unit, targeting a register file, wherein the processing unit includes two or more processing slices, each processing slice including a corresponding history buffer and at least a portion of a register file. The processing unit evicts previous result data from the register file entry to a history buffer corresponding to the processing slice, by writing new result data into the register file entry, in response to the instruction. The processing unit detects a trigger condition relating to a rollback of the processing unit to a previous state, and restores the previous result data from the history buffer to the register file entry, in response to the trigger.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: May 14, 2019
    Assignee: International Business Machines Corporation
    Inventors: Susan E. Eisen, Cliff Kucharski, Hung Q. Le, Dung Q. Nguyen, David R. Terry
  • Patent number: 10282205
    Abstract: Method and system for restoring data to a register file of a processing unit are provided. A history buffer entry (HBE) is marked for restoration to a register file entry. Result data and control information is sent from the HBE to an Issue Queue (ISQ). The ISQ issues an instruction for loading the result data into the register file entry based on the control information. A write back operation is performed to restore the result data to the register file entry, in response to issuing of the instruction.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: May 7, 2019
    Assignee: International Business Machines Corporation
    Inventors: Susan E. Eisen, Cliff Kucharski, Hung Q. Le, Dung Q. Nguyen, David R. Terry
  • Patent number: 10268518
    Abstract: Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more instruction sequencing units, where operation includes: receiving, at a load/store slice from an instruction sequencing unit, a instruction to be issued; determining, at the load/store slice, a rejection condition for the instruction; and responsive to determining the rejection condition for the instruction, maintaining state information for the instruction in the load/store slice instead of notifying the instruction sequencing unit of a rejection of the instruction.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Elizabeth A. McGlone
  • Patent number: 10255107
    Abstract: Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more instruction sequencing units, where operation includes: receiving, at a load/store slice from an instruction sequencing unit, a instruction to be issued; determining, at the load/store slice, a rejection condition for the instruction; and responsive to determining the rejection condition for the instruction, maintaining state information for the instruction in the load/store slice instead of notifying the instruction sequencing unit of a rejection of the instruction.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sundeep Chadha, Robert A. Cordes, David A. Hrusecky, Hung Q. Le, Elizabeth A. McGlone
  • Patent number: 10241800
    Abstract: A split level history buffer in a central processing unit is provided. A history buffer is partitioned into a first portion and a second portion, wherein the first portion includes a first tagged instruction. A result is generated for the first tagged instruction. A determination whether a second tagged instruction is to be stored in the first portion of the history buffer is made. Responsive to the determination that the second tagged instruction is to be stored in the first portion of the history buffer, the first tagged instruction and the generated result for the first tagged instruction is written to the second portion of the history buffer.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Hung Q. Le, Dung Q. Nguyen, David R. Terry
  • Patent number: 10223266
    Abstract: A load store unit (LSU) in a processor core detects that new data produced by the processor core is ready to be drained to an L2 cache. In response to the LSU detecting that an earlier version of the new data is not stored in L1 cache, a memory controller sends the new data as L1 cache missed data to a store queue (STQ), where the STQ makes data available for deallocation from the STQ to the L2 cache. In response to determining that there is no newer data waiting to be stored in the STQ, or no cache line invalidate to the line containing the store data in the STQ that misses the cache, the memory controller maintains the new data in the STQ with a zombie stat bit that indicates that the new data is a zombie store entry that can be utilized by the processor core.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Robert A. Cordes, Hung Q. Le, Brian W. Thompto
  • Publication number: 20190042238
    Abstract: Managing an issue queue for fused instructions and paired instructions in a microprocessor including dispatching a fused instruction to a first entry in a double issue queue; dispatching two paired instructions to a second entry in the double issue queue; issuing the fused instruction during a single cycle to an execution unit in response to determining, by the issue queue logic, that the fused instruction is ready to issue; and issuing, by the issue queue logic, the first instruction of the two paired instructions to the execution unit in response to determining, by the issue queue logic, that the first instruction of the two paired instructions is ready to issue.
    Type: Application
    Filed: August 2, 2017
    Publication date: February 7, 2019
    Inventors: MICHAEL J. GENDEN, HUNG Q. LE, DUNG Q. NGUYEN, BRIAN W. THOMPTO
  • Publication number: 20190042239
    Abstract: Managing an issue queue for fused instructions and paired instructions in a microprocessor including dispatching a fused instruction to a first entry in a double issue queue; dispatching two paired instructions to a second entry in the double issue queue; issuing the fused instruction during a single cycle to an execution unit in response to determining, by the issue queue logic, that the fused instruction is ready to issue; and issuing, by the issue queue logic, the first instruction of the two paired instructions to the execution unit in response to determining, by the issue queue logic, that the first instruction of the two paired instructions is ready to issue.
    Type: Application
    Filed: October 27, 2017
    Publication date: February 7, 2019
    Inventors: MICHAEL J. GENDEN, HUNG Q. LE, DUNG Q. NGUYEN, BRIAN W. THOMPTO
  • Publication number: 20190018679
    Abstract: Converting program instructions for two-stage processors including receiving, by a preprocessing unit, a group of program instructions; determining, by the preprocessing unit, that at least two of the group of program instructions can be converted into a single combined instruction; converting, by the preprocessing unit, the at least two program instructions into the single combined instruction comprising an extension opcode, wherein the extension opcode indicates, to an execution unit, a format of the single combined instruction; and sending, by the preprocessing unit, the single combined instruction to the execution unit.
    Type: Application
    Filed: October 27, 2017
    Publication date: January 17, 2019
    Inventors: GILES R. FRAZIER, HUNG Q. LE, JOSE E. MOREIRA, BRIAN W. THOMPTO
  • Publication number: 20190018677
    Abstract: Converting program instructions for two-stage processors including receiving, by a preprocessing unit, a group of program instructions; determining, by the preprocessing unit, that at least two of the group of program instructions can be converted into a single combined instruction; converting, by the preprocessing unit, the at least two program instructions into the single combined instruction comprising an extension opcode, wherein the extension opcode indicates, to an execution unit, a format of the single combined instruction; and sending, by the preprocessing unit, the single combined instruction to the execution unit.
    Type: Application
    Filed: July 11, 2017
    Publication date: January 17, 2019
    Inventors: GILES R. FRAZIER, HUNG Q. LE, JOSE E. MOREIRA, BRIAN W. THOMPTO
  • Publication number: 20190012175
    Abstract: Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.
    Type: Application
    Filed: August 30, 2018
    Publication date: January 10, 2019
    Inventors: Susan E. Eisen, Hung Q. Le, Bryan J. Lloyd, Dung Q. Nguyen, David S. Ray, Benjamin W. Stolt, Shih-Hsiung S. Tung
  • Publication number: 20180349141
    Abstract: A system and process for managing thread transitions includes providing two data register sets coupled to a processor and using, by the processor, the two register sets as first-level registers for thread execution. A determination is made whether a quantity of the first-level registers needed to execute one or more threads exceeds a quantity of the first-level registers of the two data register sets. Responsive to determining that the quantity of the first-level registers needed to execute the one or more threads exceeds the quantity of the first-level registers of the two data register sets, a portion of main memory or cache memory is assigned as second-level registers where the second-level registers serve as registers of at least one of the two data register sets for executing the one or more threads.
    Type: Application
    Filed: August 11, 2018
    Publication date: December 6, 2018
    Inventors: Christopher M. Abernathy, Mary D. Brown, Susan E. Eisen, James A. Kahle, Hung Q. Le, Dung Q. Nguyen