Patents by Inventor Hung Q. Le

Hung Q. Le has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11301254
    Abstract: A method, system, and/or processor for processing data is disclosed that includes processing a parent stream, detecting a branch instruction in the parent stream, activating an additional child stream, copying the content of a parent mapper copy of the parent stream to an additional child mapper copy, dispatching instructions for the parent stream and the additional child stream, and executing the parent stream and the additional child stream on different execution slices. In an aspect, a first parent mapper copy is associated and used in connection with executing the parent stream and a second different child mapper copy is associated and used in connection with executing the additional child stream. The method in an aspect includes processing one or more streams and/or one or more threads of execution on one or more execution slices.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: April 12, 2022
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Battle, Joshua W. Bowman, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto
  • Patent number: 11275614
    Abstract: A computer system includes a processor, main memory, and controller. The processor includes a plurality of hardware threads configured to execute a plurality of software threads. The main memory includes a first register table configured to contain a current set of architected registers for the currently running software threads. The controller is configured to change a first number of the architected registers assigned to a given one of the software threads to a second number of architected registers when a result of monitoring current usage of the registers by the software threads indicates that the change will improve performance of the computer system. The processor includes a second register table configured to contain a subset of the architected registers and a mapping table for each software thread indicating whether the architected registers referenced by the corresponding software thread are located in the first register table or the second register table.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: March 15, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harold W. Cain, III, Hubertus Franke, Charles R. Johns, Hung Q. Le, Ravi Nair, James A. Kahle
  • Patent number: 11275576
    Abstract: Techniques are provided for updating firmware of an accessory device. An accessory development kit of the accessory device can communicate with an accessory update daemon using a home management daemon of a controller device. Based on a firmware update policy of the accessory device, the accessory update daemon will check for firmware updates. When firmware updates are available, the accessory update daemon can instruct the home management daemon to stage the update. The home management daemon will notify the accessory development kit to be in a stage mode. The accessory update daemon will download the firmware update and send the firmware update to the accessory development kit of the accessory device using an interface for the secure channel provided by the home management daemon. The accessory device can be a third party accessory device that does not have its own firmware updating application.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: March 15, 2022
    Assignee: Apple Inc.
    Inventors: Hung Q. Le, Zaka Ur Rehman Ashraf, Keith W. Rauenbuehler, Christopher B. Zimmermann, Keith R. Bisset, Sivaramachandran Ganesan, Wayne A. Lee, Praveen Chegondi, Patrick L. Coffman
  • Patent number: 11256507
    Abstract: A system and process for managing thread execution includes providing two data register sets coupled to a processor and using, by the processor, the two register sets as first-level registers for thread execution. A portion of main memory or cache memory is assigned as second-level registers where the second-level registers serve as registers of at least one of the two data register sets for executing the threads. Data for the threads may be moved between the first-level registers and second-level registers for different modes of thread processing.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: February 22, 2022
    Assignee: International Business Machines Corporation
    Inventors: Christopher M. Abernathy, Mary D. Brown, Susan E. Eisen, James A. Kahle, Hung Q. Le, Dung Q. Nguyen
  • Publication number: 20220050682
    Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.
    Type: Application
    Filed: August 27, 2021
    Publication date: February 17, 2022
    Inventors: Brian W. Thompto, Maarten J. Boersma, Andreas Wagner, Jose E. Moreira, Hung Q. Le, Silvia Melitta Mueller, Dung Q. Nguyen
  • Publication number: 20210397435
    Abstract: Techniques are provided for updating firmware of an accessory device. An accessory development kit of the accessory device can communicate with an accessory update daemon using a home management daemon of a controller device. Based at least in part on a firmware update policy of the accessory device, the accessory update daemon will check for firmware updates. When firmware updates are available, the accessory update daemon can instruct the home management daemon to stage the update. The home management daemon will notify the accessory development kit to be in a stage mode. The accessory update daemon will download the firmware update and send the firmware update to the accessory development kit of the accessory device using an interface for the secure channel provided by the home management daemon. The accessory device can be a third party accessory device that does not have its own firmware updating application.
    Type: Application
    Filed: June 3, 2021
    Publication date: December 23, 2021
    Applicant: Apple Inc.
    Inventors: Hung Q. Le, Zaka Ur Rehman Ashraf, Keith W. Rauenbuehler, Christopher B. Zimmermann, Keith R. Bisset, Sivaramachandran Ganesan, Wayne A. Lee, Praveen Chegondi, Patrick L. Coffman
  • Publication number: 20210397436
    Abstract: Techniques are provided for updating firmware of an accessory device. An accessory development kit of the accessory device can communicate with an accessory update daemon using a home management daemon of a controller device. Based at least in part on a firmware update policy of the accessory device, the accessory update daemon will check for firmware updates. When firmware updates are available, the accessory update daemon can instruct the home management daemon to stage the update. The home management daemon will notify the accessory development kit to be in a stage mode. The accessory update daemon will download the firmware update and send the firmware update to the accessory development kit of the accessory device using an interface for the secure channel provided by the home management daemon. The accessory device can be a third party accessory device that does not have its own firmware updating application.
    Type: Application
    Filed: June 3, 2021
    Publication date: December 23, 2021
    Applicant: Apple Inc.
    Inventors: Hung Q. Le, Zaka Ur Rehman Ashraf, Keith W. Rauenbuehler, Christopher B. Zimmermann, Keith R. Bisset, Sivaramachandran Ganesan, Wayne A. Lee, Praveen Chegondi, Patrick L. Coffman
  • Publication number: 20210397432
    Abstract: Techniques are provided for updating firmware of an accessory device. An accessory development kit of the accessory device can communicate with an accessory update daemon using a home management daemon of a controller device. Based on a firmware update policy of the accessory device, the accessory update daemon will check for firmware updates. When firmware updates are available, the accessory update daemon can instruct the home management daemon to stage the update. The home management daemon will notify the accessory development kit to be in a stage mode. The accessory update daemon will download the firmware update and send the firmware update to the accessory development kit of the accessory device using an interface for the secure channel provided by the home management daemon. The accessory device can be a third party accessory device that does not have its own firmware updating application.
    Type: Application
    Filed: December 3, 2020
    Publication date: December 23, 2021
    Applicant: Apple Inc.
    Inventors: Hung Q. Le, Zaka Ur Rehman Ashraf, Keith W. Rauenbuehler, Christopher B. Zimmermann, Keith R. Bisset, Sivaramachandran Ganesan, Wayne A. Lee, Praveen Chegondi, Patrick L. Coffman
  • Patent number: 11188340
    Abstract: Techniques for parallel execution of instructions in an instruction set are described. The techniques include determining a plurality of instruction streams and paths for a branch in an instruction set and executing the determined paths in parallel such that a mis-predicted path does not cause significant mis-prediction penalties.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: November 30, 2021
    Assignee: International Business Machines Corporation
    Inventors: Brian W. Thompto, Hung Q. Le, Dung Q. Nguyen
  • Patent number: 11157276
    Abstract: A computer system, processor, and method for processing information is disclosed. The system, processor and/or method includes at least one computer processor; a register file associated with the at least one processor, the register file having a plurality of entries for storing data where a whole entry has two halves, the register file having multiple ports to write data to the register file and multiple ports to read data from the register file; and one or more execution units associated with the register file, the execution units configured to read data from the register file and to write data to the register file, wherein the processor is configured to write either scalar data or vector data to a single register file entry.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: October 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Battle, Maarten J. Boersma, Niels Fricke, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto
  • Patent number: 11144323
    Abstract: Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: October 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sam G. Chu, Markus Kaltenbach, Hung Q. Le, Jentje Leenstra, Jose E. Moreira, Dung Q. Nguyen, Brian W. Thompto
  • Patent number: 11132198
    Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Brian W. Thompto, Maarten J. Boersma, Andreas Wagner, Jose E. Moreira, Hung Q. Le, Silvia Melitta Mueller, Dung Q. Nguyen
  • Patent number: 11119777
    Abstract: Techniques for an extended prefix including a routing bit for an extended instruction format are described herein. An aspect includes generating, by an instruction preprocessing module, a first extended instruction corresponding to an internal operation including a first routing bit. Another aspect includes generating, by the instruction preprocessing module, a second extended instruction corresponding to a prefixed instruction set architecture (ISA) instruction including a second routing bit, wherein a value of the second routing bit is opposite a value of the first routing bit. Another aspect includes providing the first extended instruction and the second extended instruction to a central processing unit (CPU). Another aspect includes, based on the value of the first routing bit, routing the internal operation directly to an execution unit of the CPU, and based on the value of the second routing bit, routing the prefixed ISA instruction to a decode/execute path of the CPU.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: September 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Giles Roger Frazier, Hung Q. Le
  • Patent number: 11119774
    Abstract: A system and/or method for processing information is disclosed that has at least one processor; a register file associated with the processor, the register file sliced into a plurality of STF blocks having a plurality of STF entries, and in an embodiment, each STF block is further partitioned into a plurality of sub-blocks, each sub-block having a different portion of the plurality of STF entries; and a plurality of execution units configured to read data from and write data to the register file, where the plurality of execution units are arranged in one or more execution slices. In one or more embodiments, the system is configured so that each execution slice has a plurality of STF blocks, and alternatively or additionally, each of the plurality of execution units in a single execution slice is assigned to write to one, and preferably only one, of the plurality of STF blocks.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Brian W. Thompto, Dung Q. Nguyen, Hung Q. Le, Sam Gat-Shang Chu
  • Patent number: 11119772
    Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one processor having a main register file, the main register file having a plurality of entries for storing data; one or more execution units including a dense math execution unit; and at least one accumulator register file, the at least one accumulator register file associated with the dense math execution unit. The processor in an embodiment is configured to process data in the dense math execution unit where the results of the dense math execution unit are written to a first group of one or more accumulator register file entries, and after a checkpoint boundary is crossed based upon, for example, the number ā€œNā€ of instructions dispatched after the start of the checkpoint, the results of the dense math execution unit are written to a second group of one or more accumulator register file entries.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Steven J Battle, Brian D. Barrick, Susan E. Eisen, Andreas Wagner, Dung Q. Nguyen, Brian W. Thompto, Hung Q. Le, Kenneth L. Ward
  • Patent number: 11106466
    Abstract: A computer processor includes an issue queue to receive an instruction, and one or more execution units to generate a condition code bit corresponding to the instruction. A branch condition queue is in signal communication with the issue queue, and receives the instruction from the issue queue before the at least one execution unit generates the condition code bit.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: August 31, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicholas R. Orzol, Michael J. Genden, Hung Q. Le, Dung Q. Nguyen, Eula Faye A. Tolentino, Brian W. Thompto
  • Patent number: 11093246
    Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor, a register file associated with the at least one processor, the register file having a plurality of entries for storing data and sliced into a plurality of register banks, each register bank having a portion of the plurality of entries for storing data, one or more write ports to write data to the register file entries, and a plurality of read ports to read data from the register file entries; one or more read multiplexors associated with one or more read ports of each register bank and configured to receive data from the respective register banks; and one or more write multiplexors associated with one or more of the register banks.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: August 17, 2021
    Assignee: International Business Machines Corporation
    Inventors: Maarten J. Boersma, Niels Fricke, Michael Klaus Kroener, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto
  • Patent number: 11093282
    Abstract: A non-limiting example of a computer-implemented method for file register writes using pointers includes, responsive to a dispatch instruction, storing, at a location in a history buffer, an instruction tag and first data associated with the instruction tag. The method further includes storing a pointer in an issue queue. The pointer points to the location in the history buffer. The method further includes performing a write back of second data using the pointer stored in the issue queue. The write back writes the second data into the location of the history buffer associated with the pointer.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: August 17, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian D. Barrick, Steven J. Battle, Joshua W. Bowman, Cliff Kucharski, Hung Q. Le, Dung Q. Nguyen, David R. Terry
  • Patent number: 11061681
    Abstract: A method, system, and/or processor for processing data is disclosed that includes processing a parent stream; detecting a branch instruction in the parent stream; activating an additional child stream; setting a copy select vector of the child stream to be the same as the copy select vector of the parent stream; dispatching instructions for the parent stream and the additional child stream, and executing the parent stream and the additional child stream on different execution slices. In an aspect, the method further includes setting the copy select bits in the copy select vector for the child stream to equal the copy select bits in the copy select vector for the parent stream. A first parent mapper copy in an embodiment is associated and used in connection with executing the parent stream and a second different child mapper copy is associated and used in connection with executing the additional child stream.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Battle, Joshua W. Bowman, Hung Q. Le, Dung Q Nguyen, Brian W. Thompto
  • Publication number: 20210173649
    Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one processor having a main register file, the main register file having a plurality of entries for storing data; one or more execution units including a dense math execution unit; and at least one accumulator register file, the at least one accumulator register file associated with the dense math execution unit. The processor in an embodiment is configured to process data in the dense math execution unit where the results of the dense math execution unit are written to a first group of one or more accumulator register file entries, and after a checkpoint boundary is crossed based upon, for example, the number ā€œNā€ of instructions dispatched after the start of the checkpoint, the results of the dense math execution unit are written to a second group of one or more accumulator register file entries.
    Type: Application
    Filed: December 6, 2019
    Publication date: June 10, 2021
    Inventors: Steven J Battle, Brian D. Barrick, Susan E. Eisen, Andreas Wagner, Dung Q. Nguyen, Brian W. Thompto, Hung Q. Le, Kenneth L. Ward