Abstract: A memory device includes: a memory array used for implementing neural networks (NN); and a controller coupled to the memory array. The controller is configured for: in updating and writing unrewritable data into the memory array in a training phase, marching the unrewritable data into a buffer zone of the memory array; and in updating and writing rewritable data into the memory array in the training phase, marching the rewritable data by skipping the buffer zone.

Abstract: A memory device includes an array of composite memory units. At least one of the composite memory units comprises a first memory cell of a first type, a second memory cell of a second type, a first intra-unit data path connecting the first memory cell to the second memory cell, and a first data path control switch. The first data path control switch is responsive to a data transfer enable signal which enables data transfer between the first memory cell and the second memory cell through the first intra-unit data path.

Abstract: A flash memory device and a controlling method are provided. The flash memory device includes a memory array, an in-place update module, an out-of-place update module and a latency-aware module. The in-place update module is used for performing a program procedure or a garbage collection procedure via a bit erase operation or a page erase operation on the memory array. The out-of-place update module is used for performing the program procedure or the garbage collection procedure via a block erase operation or a migration operation on the memory array. The latency-aware module is used for determining a relationship between a first overhead of the in-place update module and a second overhead of the out-of-place update module.

Abstract: A circuit for in-memory multiply-and-accumulate functions includes a plurality of NAND blocks. A NAND block includes an array of NAND strings, including B columns and S rows, and L levels of memory cells. W word lines are coupled to (B*S) memory cells in respective levels in the L levels. A source line is coupled to the (B*S) NAND strings in the block. String select line drivers supply voltages to connect NAND strings on multiple string select lines to corresponding bit lines simultaneously. Word line drivers are coupled to apply word line voltages to a word line or word lines in a selected level. A plurality of bit line drivers apply input data to the B bit lines simultaneously. A current sensing circuit is coupled to the source line.

Abstract: A brake release device and a robot manipulator employing the same are provided. The robot manipulator includes a housing and a brake element. The housing defines an inner space and has an opening, and the inner space is in communication with a space outside the housing through the opening. The brake element is disposed within the inner space. The robot manipulator stops or is allowed to actuate according to a position of the brake element. The brake release device is connected with the brake element. The brake release device is partially located in the inner space, and the brake release device partially penetrates through the opening and is exposed from the housing. When the part of the brake release device exposed from the housing is moved by an external force so as to drive the brake element to move synchronously, the robot manipulator is allowed to actuate.

Abstract: Disclosed is a management system for managing a memory device having sub-chips each having a container area and a data area. A CPU selects a target sub-chip according to respective temperature of the sub-chips. When the CPU intends to access a first original data in one of the data areas, a hot date tracking device acquires a first original address of the first original data from the CPU. When the first original address is recorded in one of a plurality of tracking layers, the CPU is indicated to access a first copied data corresponding to the first original data in the container area of the target sub-chip according to a current tracking layer recording the first original address. When the first original address is not recorded in the tracking layers, the CPU accesses the first original data in the data area according to the first original address.

Abstract: A heat dissipating system of movable robot is provided. The heat dissipating system includes a movable robot and at least one wind resistance structure. The movable robot includes a housing, at least one airflow passage and plural first air holes. The housing defines an inner space, the airflow passage is disposed in the inner space, and the first air holes are disposed on the housing and are in communication with the airflow passage respectively. When the movable robot moves, an air current is generated accordingly. The air current partially flows into the airflow passage through the first air hole acted as an inlet, and the air current in the airflow passage is released from the first air hole acted as an outlet. The wind resistance structure is configured for guiding the air current into the first air hole acted as the inlet.

Abstract: A robotic system includes a base and at least one axis actuation module. The base includes an input power conversion device. A power input terminal of the input power conversion device receives an input voltage. The input voltage is converted into a first voltage by the input power conversion device. The first voltage is outputted from a power output terminal of the input power conversion device. The at least one axis actuation module is installed on the base. Each axis actuation module includes a motor, an axis power conversion device and a driving device. The first voltage is converted into a second voltage with a rated voltage value by the axis power conversion device. The second voltage is converted into a third voltage by the driving device. The third voltage is provided to the motor.

Abstract: A processor receives, from an input device, input data for processing. Upon determining that the input data corresponds to an artificial intelligence (AI) application, the processor generates an AI command for performing read or write operations for a memory device that is configured to store data for a plurality of applications including the AI application, the AI command characterized by an operational code and including information about one or more components of the AI application corresponding to the input data. The processor sends the AI command and the input data to a storage controller managing the memory device, wherein the read or write operations for the memory device are performed by the storage controller using the operational code and the information included in the AI command. The processor receives, from the storage controller, a result of the read or write operations performed on the memory device.

Abstract: A memory controlling method, a memory controlling circuit and a memory system are provided. A memory includes a plurality of memory chips. The memory controlling method includes the following steps: The memory chips are grouped into at least two partner groups by a grouping unit. A quantity of the memory chips in each of the partner groups is at least two. At least one of the memory chips in each of the partner groups is required to serve a reading request or a writing request by a processing unit.

Abstract: Disclosed is a management system for managing a memory device having sub-chips each having a container area and a data area. A CPU selects a target sub-chip according to respective temperature of the sub-chips. When the CPU intends to access a first original data in one of the data areas, a hot date tracking device acquires a first original address of the first original data from the CPU. When the first original address is recorded in one of a plurality of tracking layers, the CPU is indicated to access a first copied data corresponding to the first original data in the container area of the target sub-chip according to a current tracking layer recording the first original address. When the first original address is not recorded in the tracking layers, the CPU accesses the first original data in the data area according to the first original address.

Abstract: A data management method for a memory device includes: counting a system time; when at least a part of a block of the memory device is accessed or refreshed or programmed at first time, assigning a block number of the block to point to a maximum remaining retention time; when a first downgrade trigger time reaches, assigning the block number to point from the maximum remaining retention time to a medium remaining retention time; when a second downgrade trigger time reaches, assigning the block number to point from the medium remaining retention time to a minimum remaining retention time; and once the block number points to the minimum remaining retention time, refreshing the block and assigning the block number to point to the maximum remaining retention time.

Abstract: A data allocating method includes steps of: determining whether data to be written into a physical memory block is hot data or cold data; when the data is hot data, according to a hot data allocating order, searching at least one first empty sub-block from the physical memory block to allocate the data; when the data is cold data, according to a cold data allocating order, searching at least one second empty sub-block from the physical memory block to allocate the data.

Abstract: A circuit test method for a test device to test a device under test is provided. The circuit test method includes the steps of applying zero volts to a plurality of power pins of the device under test; applying a test voltage to a first signal pin among a plurality of signal pins of the device under test; and measuring a current on a second signal pin among the plurality of signal pins of the device under test and determining whether there is a leakage current in the device under test.

Abstract: A method for writing data into a persistent storage device includes grouping a plurality of data entries stored in a temporary storage device to form a data unit, such that the data unit has a size equal to an integer multiple of a size of an access unit of the persistent storage device. The method further includes writing the data unit into the persistent storage device.

Abstract: A memory device includes a memory controller and a non-volatile memory communicatively coupled to the memory controller and storing a mapping table and a journal table. The memory controller is configured to write data and a logical address of the data into the non-volatile memory, load mapping information related to the logical address of the data from the mapping table of the non-volatile memory into a mapping cache of the memory controller, update the mapping cache with an updated mapping relationship between the logical address of the data and a physical address of the data, and perform a journaling operation to write the updated mapping relationship into the journal table.

Abstract: A cache system is provided. The cache system includes a first cache and a second cache. The first cache is configured for storing a first status of a plurality of data. The second cache is configured for storing a table. The table includes the plurality of data arranged from a highest level to a lowest level. The cache system is configured to update the first status of the plurality of data in the first cache. The cache system is further configured to update the table in the second cache according to the first status of the plurality of data.

Abstract: An image sensor is provided in the present invention. The image sensor includes a continuous microlens including a plurality of top sub lenses connected with one another and a plurality of bottom sub lenses disposed corresponding to the top sub lenses. The continuous microlens maybe used to enhance quantum efficiency. The top sub lens and the bottom sub lens condense light by two steps within a shorter distance and make the light focused on a sensing element, and the continuous microlens may be applied without the limitation about the size of the pixel region accordingly. Additionally, the sensitivity and the uniformity thereof may be enhanced because of the shorter distance between the bottom sub lens and the sensing element. A transmittance of a color filter layer disposed corresponding to the bottom sub lens may also be enhanced.

Abstract: A data allocating method includes steps of: determining whether data to be written into a physical memory block is hot data or cold data; when the data is hot data, according to a hot data allocating order, searching at least one first empty sub-block from the physical memory block to allocate the data; when the data is cold data, according to a cold data allocating order, searching at least one second empty sub-block from the physical memory block to allocate the data.

Abstract: A memory system is provided. The memory system includes a memory controller and a first memory block. The first memory block is configured to store a first data from a top of the first memory block in a top-down fashion. The first memory block is configured to store a first metadata corresponding to the first data from a bottom of the first memory block in a bottom-up fashion. The first data forms a first data area. The first metadata forms a first metadata area. And a first continuous space is formed between a bottom of the first data area and a top of the first metadata area.