Patents by Inventor Hung-Yueh Chen
Hung-Yueh Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12063792Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.Type: GrantFiled: June 8, 2023Date of Patent: August 13, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Po-Kai Hsu, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen, Wei Chen
-
Publication number: 20240237128Abstract: A user equipment assistance information (UAI) negotiation method, for a user equipment (UE) of mobile communication includes receiving a first OtherConfig element of an RRC reconfiguration message comprising a plurality of configuration parameters with SETUP values from a network terminal; sending a first UAI including a first value of a first configuration parameter of the configuration parameters to the network terminal; and receiving a first RRC reconfiguration message corresponding to the first UAI from the network terminal.Type: ApplicationFiled: October 3, 2023Publication date: July 11, 2024Applicant: MediaTek Singapore Pte. Ltd.Inventors: Hung-Yueh Chen, Yu-Lun Chang, Byeng Hyun Kim, JUNG SHUP SHIN, Hung-Yuan Yang, Jun-Jie Su, Kyung Hyun Ahn
-
Publication number: 20240196756Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.Type: ApplicationFiled: February 26, 2024Publication date: June 13, 2024Applicant: United Microelectronics Corp.Inventors: Hui-Lin Wang, Wei Chen, Po-Kai Hsu, Yu-Ping Wang, Hung-Yueh Chen
-
Publication number: 20240196759Abstract: A method of manufacturing a magnetoresistive random access memory, including forming a conductive plug in a substrate, forming a bottom electrode material layer, a magnetic tunnel junction material layer and a top electrode material layer on the substrate and the conductive plug, and performing an anisotropic etch process to pattern the bottom electrode material layer, the magnetic tunnel junction material layer and the top electrode material layer, thereby forming a magnetic memory cell on the conductive plug, wherein the anisotropic etch process overetches the conductive plug and the substrate so that a notched portion is formed on one side of an upper edge of the conductive plug, and depressed regions are formed on the substrate at two sides of the magnetic memory cell.Type: ApplicationFiled: February 21, 2024Publication date: June 13, 2024Applicant: UNITE MICROELECTRONICS CORP.Inventors: Hung-Chan Lin, Yu-Ping Wang, Hung-Yueh Chen
-
Publication number: 20240172456Abstract: A method of manufacturing a hybrid random access memory in a system-on-chip, including steps of providing a semiconductor substrate with a magnetoresistive random access memory (MRAM) region and a resistive random-access memory (ReRAM) region, forming multiple ReRAM cells in the ReRAM region on the semiconductor substrate, forming a first dielectric layer on the semiconductor substrate, wherein the ReRAM cells are in the first dielectric layer, forming multiple MRAM cells in the MRAM region on the first dielectric layer, and forming a second dielectric layer on the first dielectric layer, wherein the MRAM cells are in the second dielectric layer.Type: ApplicationFiled: January 23, 2024Publication date: May 23, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Po-Kai Hsu, Hui-Lin Wang, Ching-Hua Hsu, Yi-Yu Lin, Ju-Chun Fan, Hung-Yueh Chen
-
Publication number: 20240143050Abstract: A portable electronic device includes a housing, a heat-dissipation component, a bracket, a door structure, a driving mechanism, and a driven linkage. The housing includes a heat-dissipation opening disposed in the housing. The bracket is disposed in the housing and surrounds the heat-dissipation component. The door structure is configured to move between a closed position covering the heat-dissipation opening and an open position exposing the heat-dissipation opening. The driving mechanism is coupled between the bracket and the door structure to drive the door structure to rotate and move. The driven linkage is coupled between the bracket and the door structure. When the door structure is driven to rotate and move, the door structure drives the driven linkage to rotate and move, so that the driven linkage and the driving mechanism jointly drive the door structure to move between the closed position and the open position.Type: ApplicationFiled: June 13, 2023Publication date: May 2, 2024Applicant: ASUSTeK COMPUTER INC.Inventors: Cheng-Han Chung, Hung-Yueh Chen, Ching-Yuan Yang
-
Publication number: 20240138018Abstract: A user equipment assistance information (UAI) negotiation method, for a user equipment (UE) of mobile communication includes receiving a first OtherConfig element of an RRC reconfiguration message comprising a plurality of configuration parameters with SETUP values from a network terminal; sending a first UAI including a first value of a first configuration parameter of the configuration parameters to the network terminal; and receiving a first RRC reconfiguration message corresponding to the first UAI from the network terminal.Type: ApplicationFiled: October 2, 2023Publication date: April 25, 2024Applicant: MediaTek Singapore Pte. Ltd.Inventors: Hung-Yueh Chen, Yu-Lun Chang, Byeng Hyun Kim, JUNG SHUP SHIN, Hung-Yuan Yang, Jun-Jie Su, Kyung Hyun Ahn
-
Publication number: 20240129766Abstract: A throttle control method for a mobile device include collecting input data, generating a first set of user experience indices according to the input data, and checking whether a user experience index of the first set of user experience indices satisfies a UEI threshold. The input data includes common information data, current configuration data and a plurality of throttle control parameters. Each user experience index of the first set of user experience indices is corresponding to at least one of throttle control parameter of the plurality of throttle control parameters.Type: ApplicationFiled: April 10, 2023Publication date: April 18, 2024Applicant: MediaTek Singapore Pte. Ltd.Inventors: Hung-Yueh Chen, Byeng Hyun Kim, JUNG SHUP SHIN, Shih-Hsin Chen, Chih-Chieh Lai, Chung-Pi Lee, JUNGWOO LEE, Yu-Lun Chang
-
Publication number: 20240130141Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.Type: ApplicationFiled: December 25, 2023Publication date: April 18, 2024Applicant: United Microelectronics Corp.Inventors: Ya-Huei Tsai, Rai-Min Huang, Yu-Ping Wang, Hung-Yueh Chen
-
Publication number: 20240130246Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.Type: ApplicationFiled: December 25, 2023Publication date: April 18, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
-
Patent number: 11957061Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.Type: GrantFiled: May 23, 2023Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Yi-Yu Lin, Ching-Hua Hsu, Hung-Yueh Chen
-
Patent number: 11950513Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.Type: GrantFiled: July 5, 2022Date of Patent: April 2, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Wei Chen, Po-Kai Hsu, Yu-Ping Wang, Hung-Yueh Chen
-
Patent number: 11944016Abstract: A magnetoresistive random access memory, including a substrate, a conductive plug in the substrate, wherein the conductive plug has a notched portion on one side of the upper edge of the conductive plug, and a magnetic memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction on the bottom electrode and a top electrode on the magnetic tunnel junction, wherein the bottom surface of the magnetic memory cell and the top surface of the conductive plug completely align and overlap each other.Type: GrantFiled: March 11, 2022Date of Patent: March 26, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hung-Chan Lin, Yu-Ping Wang, Hung-Yueh Chen
-
Patent number: 11925035Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.Type: GrantFiled: October 26, 2022Date of Patent: March 5, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Kai Hsu, Hui-Lin Wang, Ching-Hua Hsu, Yi-Yu Lin, Ju-Chun Fan, Hung-Yueh Chen
-
Patent number: 11895848Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.Type: GrantFiled: May 22, 2022Date of Patent: February 6, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ya-Huei Tsai, Rai-Min Huang, Yu-Ping Wang, Hung-Yueh Chen
-
Patent number: 11895926Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.Type: GrantFiled: November 3, 2020Date of Patent: February 6, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
-
Publication number: 20240015700Abstract: The invention provides a method for multi-paging of a user equipment (UE) in a network; the network may be a wireless cellular network, and may comprise a plurality of cells. The method may be executed by the UE, and may comprise a multi-paging procedure. The multi-paging procedure may comprise: when the UE camps on a serving cell of the plurality of cells, checking whether a non-serving cell paging message is received on a non-serving cell of the plurality of cells, with the non-serving cell being different from the serving cell.Type: ApplicationFiled: April 12, 2023Publication date: January 11, 2024Inventors: Hung-Yueh CHEN, Hung-Wei SHIH, Byeng Hyun Kim, JUNG SHUP SHIN, Kyung Hyun Ahn, Amit Kumar Shukla
-
Publication number: 20230403941Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to and directly contacting the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is a single layer structure made of dielectric material and an edge of the cap layer contacts the first IMD layer directly.Type: ApplicationFiled: August 27, 2023Publication date: December 14, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Po-kai Hsu, Hung-Yueh Chen, Yu-Ping Wang
-
Patent number: 11800723Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a first diffusion region and a second diffusion region extending along a first direction on a substrate, a first contact plug extending along a second direction from the first diffusion region to the second diffusion region on the substrate, a first gate pattern and a second gate pattern extending along the second direction adjacent to one side of the first contact plug, and a third gate pattern and a fourth gate pattern extending along the second direction adjacent to another side of the first contact plug.Type: GrantFiled: September 13, 2020Date of Patent: October 24, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: I-Fan Chang, Hung-Yueh Chen, Rai-Min Huang, Jia-Rong Wu, Yu-Ping Wang
-
Publication number: 20230329006Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.Type: ApplicationFiled: June 8, 2023Publication date: October 12, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Po-Kai Hsu, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen, Wei Chen