Abstract: A namespace among one or more namespaces in a memory system may be manage on the basis of a write pointer and a write count. The namespace may be managed by a memory controller of the memory system. The memory system may set the one or more namespaces, and may set, for each namespace, a write pointer indicating a position where a new data unit is to be written in that namespace and a write count indicating the number of times a data unit has been written or updated in that namespace. The memory system may determine to migrate one or more data units in a namespace based on the write pointer and the write count of that namespace.

Abstract: According to the present technology, a memory system includes a plurality of memory devices each including a plurality of memory blocks, and a memory controller configured to receive information for target performance from an outside and a return request of achievement information indicating whether the target performance is achievable and including group information on each size of one or more necessary groups for achieving the target performance, provide the achievement information to the outside in response to the return request, and allocate memory blocks to the necessary groups based on the achievement information.

Abstract: A memory controller includes a block ratio calculator configured to calculate a ratio of free blocks among memory blocks for storing data; a policy selector configured to select, based on the calculated ratio of free blocks, any one garbage collection policy of a first garbage collection policy of specifying priorities to be used to select a victim block depending on attributes of the data, and a second garbage collection policy of specifying the priorities to be used to select the victim block regardless of the attributes of the data; and a garbage collection performing component configured to perform a garbage collection operation on at least one memory block of the memory blocks according to the garbage collection policy selected by the policy selector.

Abstract: A namespace among one or more namespaces in a memory system may be manage on the basis of a write pointer and a write count. The namespace may be managed by a memory controller of the memory system. The memory system may set the one or more namespaces, and may set, for each namespace, a write pointer indicating a position where a new data unit is to be written in that namespace and a write count indicating the number of times a data unit has been written or updated in that namespace. The memory system may determine to migrate one or more data units in a namespace based on the write pointer and the write count of that namespace.

Abstract: A storage device includes: a memory device including a plurality of memory blocks organized into a plurality of zones; and a memory controller configured to perform a write operation on the plurality of zones. The memory controller is operable to divide at least one zone among the plurality of zones into subzones when the memory controller receives data corresponding to consecutive logical addresses provided from a host, and control the memory device to store the data in at least one subzone among the subzones. The at least one zone can be divided based on a characteristic of the memory device and a size of the data.

Abstract: A memory controller includes a block ratio calculator configured to calculate a ratio of free blocks among memory blocks for storing data; a policy selector configured to select, based on the calculated ratio of free blocks, any one garbage collection policy of a first garbage collection policy of specifying priorities to be used to select a victim block depending on attributes of the data, and a second garbage collection policy of specifying the priorities to be used to select the victim block regardless of the attributes of the data; and a garbage collection performing component configured to perform a garbage collection operation on at least one memory block of the memory blocks according to the garbage collection policy selected by the policy selector.

Abstract: A memory controller includes a block ratio calculator configured to calculate a ratio of free blocks among memory blocks for storing data; a policy selector configured to select, based on the calculated ratio of free blocks, any one garbage collection policy of a first garbage collection policy of specifying priorities to be used to select a victim block depending on attributes of the data, and a second garbage collection policy of specifying the priorities to be used to select the victim block regardless of the attributes of the data; and a garbage collection performing component configured to perform a garbage collection operation on at least one memory block of the memory blocks according to the garbage collection policy selected by the policy selector.

Abstract: A controller for controlling a memory devices is provided to include: a first core configured to control first memory dies; a second core configured to control second memory dies; and a host interface configured to: receive submission queue tail pointers and command information on each of commands corresponding to the tail pointers from host, classify the commands into a first address command associated with a first logical address and a second address command associated with a second logical address based on the command information, fetch the first and second address commands from host, and provide the first address command to the first core and the second address command to the second core based on the processing order of the first and second address commands determined based on status of the first memory dies and the second memory dies.

Abstract: A data processing system is provided to include a memory system to store data and information; and a host in communication with the memory system and including a submission queue for queueing a command to be processed by the memory system, the host configured to provide the memory system with a submission queue tail pointer indicating a tail of the submission queue and command information on a command, wherein the memory system is configured to receive command information on the command, performs a pre-operation on the command based on the command information, and fetches the command from the submission queue based on a result of the pre-operation.

Abstract: A controller for controlling memory devices is provided to include: a first core configured to control first memory devices in communication with the controller and configured to store data associated with first logical addresses; a second core configured to control second memory devices in communication with the controller and configured to store data associated with second logical addresses; and a host interface configured to (1) queue commands received from a host in a queue, (2) perform a command reordering that determines a processing order of queued commands including a first address command associated with a first logical address and a second address command associated with a second logical address based on statuses of the first memory devices and the second memory devices, and (3) provide the first address command to the first core and the second address command to the second core based on the processing order.

Abstract: A storage device includes: a memory device including a plurality of memory blocks organized into a plurality of zones; and a memory controller configured to perform a write operation on the plurality of zones. The memory controller is operable to divide at least one zone among the plurality of zones into subzones when the memory controller receives data corresponding to consecutive logical addresses provided from a host, and control the memory device to store the data in at least one subzone among the subzones. The at least one zone can be divided based on a characteristic of the memory device and a size of the data.

Abstract: A memory controller controls a memory device including a memory cell array, and includes: a message information generator configured to receive a first request message from a host, and generate and output response characteristic information indicating a type of the first request message that defines a response time within which a message response to the first request message is provided to the host and a response output controller configured to determine, based on the response characteristic information, a time at which the message response corresponding to the first request message is output to the host.

Abstract: A controller for controlling memory devices is provided to include: a first core configured to control first memory devices in communication with the controller and configured to store data associated with first logical addresses; a second core configured to control second memory devices in communication with the controller and configured to store data associated with second logical addresses; and a host interface configured to (1) queue commands received from a host in a queue, (2) perform a command reordering that determines a processing order of queued commands including a first address command associated with a first logical address and a second address command associated with a second logical address based on statuses of the first memory devices and the second memory devices, and (3) provide the first address command to the first core and the second address command to the second core based on the processing order.

Abstract: A data processing system is provided to include a memory system to store data and information; and a host in communication with the memory system and including a submission queue for queueing a command to be processed by the memory system, the host configured to provide the memory system with a submission queue tail pointer indicating a tail of the submission queue and command information on a command, wherein the memory system is configured to receive command information on the command, performs a pre-operation on the command based on the command information, and fetches the command from the submission queue based on a result of the pre-operation.

Abstract: A controller for controlling a memory devices is provided to include: a first core configured to control first memory dies; a second core configured to control second memory dies; and a host interface configured to: receive submission queue tail pointers and command information on each of commands corresponding to the tail pointers from host, classify the commands into a first address command associated with a first logical address and a second address command associated with a second logical address based on the command information, fetch the first and second address commands from host, and provide the first address command to the first core and the second address command to the second core based on the processing order of the first and second address commands determined based on status of the first memory dies and the second memory dies.

Abstract: A memory system includes a memory device including a plurality of memory dies and a controller coupled to the plurality of memory dies via plural data paths. The controller is configured to select a first path among the plural data paths, activate unselected paths among the plural data paths, and perform a calibration operation for data communication between the controller and a first memory die coupled to the controller via the first path among the plural memory dies while the unselected paths are activated.

Abstract: A memory controller includes a block ratio calculator configured to calculate a ratio of free blocks among memory blocks for storing data; a policy selector configured to select, based on the calculated ratio of free blocks, any one garbage collection policy of a first garbage collection policy of specifying priorities to be used to select a victim block depending on attributes of the data, and a second garbage collection policy of specifying the priorities to be used to select the victim block regardless of the attributes of the data; and a garbage collection performing component configured to perform a garbage collection operation on at least one memory block of the memory blocks according to the garbage collection policy selected by the policy selector.

Abstract: A memory controller includes a block ratio calculator configured to calculate a ratio of free blocks among memory blocks for storing data; a policy selector configured to select, based on the calculated ratio of free blocks, any one garbage collection policy of a first garbage collection policy of specifying priorities to be used to select a victim block depending on attributes of the data, and a second garbage collection policy of specifying the priorities to be used to select the victim block regardless of the attributes of the data; and a garbage collection performing component configured to perform a garbage collection operation on at least one memory block of the memory blocks according to the garbage collection policy selected by the policy selector.

Abstract: A memory controller includes a block ratio calculator configured to calculate a ratio of free blocks among memory blocks for storing data; a policy selector configured to select, based on the calculated ratio of free blocks, any one garbage collection policy of a first garbage collection policy of specifying priorities to be used to select a victim block depending on attributes of the data, and a second garbage collection policy of specifying the priorities to be used to select the victim block regardless of the attributes of the data; and a garbage collection performing component configured to perform a garbage collection operation on at least one memory block of the memory blocks according to the garbage collection policy selected by the policy selector.

Abstract: A memory controller controls a memory device including a memory cell array, and includes: a message information generator configured to receive a first request message from a host, and generate and output response characteristic information indicating a type of the first request message that defines a response time within which a message response to the first request message is provided to the host and a response output controller configured to determine, based on the response characteristic information, a time at which the message response corresponding to the first request message is output to the host.