Patents by Inventor Hwa-Chyi Chiou
Hwa-Chyi Chiou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11894674Abstract: A power detection circuit is provided. The protection circuit is coupled to a pad and includes a trigger circuit and a discharge circuit. The trigger circuit includes a first transistor of a first conductivity type and a second transistor, also of the first conductivity type, which are coupled in series between the pad and a ground terminal. The trigger circuit detects whether a transient even occurs on the pad. The discharge circuit is coupled between the bonding pad and the ground terminal and controlled by the trigger circuit. In response to the transient event occurring on the bonding pad, the trigger circuit generates a trigger voltage to trigger the discharge circuit to provide a discharge path between the pad and the ground terminal.Type: GrantFiled: May 11, 2022Date of Patent: February 6, 2024Assignee: Vanguard International Semiconductor CorporationInventors: Jian-Hsing Lee, Yeh-Ning Jou, Chih-Hsuan Lin, Chang-Min Lin, Hwa-Chyi Chiou
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Publication number: 20240028813Abstract: A semiconductor layout including a semiconductor layer and a dummy layer is provided. The semiconductor layer includes a layout pattern. The dummy layer includes a dummy pattern. A check circuit calculates the layout pattern and the dummy pattern to generate a calculated value. The check circuit compares the calculated value to the predetermined value to determine whether the layout pattern has been modified.Type: ApplicationFiled: July 25, 2022Publication date: January 25, 2024Applicant: Vanguard International Semiconductor CorporationInventors: Yeh-Ning JOU, Chih-Hsuan LIN, Shu-Pin HSU, Hwa-Chyi CHIOU, Chang-Min LIN, Tsong-Shyan CHEN
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Publication number: 20230369848Abstract: A power detection circuit is provided. The protection circuit is coupled to a pad and includes a trigger circuit and a discharge circuit. The trigger circuit includes a first transistor of a first conductivity type and a second transistor, also of the first conductivity type, which are coupled in series between the pad and a ground terminal. The trigger circuit detects whether a transient even occurs on the pad. The discharge circuit is coupled between the bonding pad and the ground terminal and controlled by the trigger circuit. In response to the transient event occurring on the bonding pad, the trigger circuit generates a trigger voltage to trigger the discharge circuit to provide a discharge path between the pad and the ground terminal.Type: ApplicationFiled: May 11, 2022Publication date: November 16, 2023Applicant: Vanguard International Semiconductor CorporationInventors: Jian-Hsing LEE, Yeh-Ning JOU, Chih-Hsuan LIN, Chang-Min LIN, Hwa-Chyi CHIOU
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Patent number: 11810872Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first drain conductive element of the source protective circuit partially overlaps a first source conductive element of the drain protective circuit.Type: GrantFiled: August 29, 2022Date of Patent: November 7, 2023Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Jian-Hsing Lee, Shao-Chang Huang, Chih-Hsuan Lin, Yu-Kai Wang, Karuna Nidhi, Hwa-Chyi Chiou
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Publication number: 20230343780Abstract: An electrostatic discharge (ESD) protection structure including a P-type substrate, a P-type structure, an N-type buried layer, an element active region, a P-type guard ring, and an N-type structure is provided. The P-type structure is formed in the P-type substrate and serves as an electrical contact of the P-type substrate. The N-type buried layer is formed in the P-type substrate. The element active region is formed on the N-type buried layer. The P-type guard ring is formed on the N-type buried layer and surrounds the element active region. The N-type structure is formed on the N-type buried layer and disposed between the P-type guard ring and the P-type structure.Type: ApplicationFiled: April 20, 2022Publication date: October 26, 2023Applicant: Vanguard International Semiconductor CorporationInventors: Chang-Min LIN, Chih-Hsuan LIN, Yeh-Ning JOU, Hwa-Chyi CHIOU, Jian-Hsing LEE
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Patent number: 11728644Abstract: An electronic device including a first transistor, a second transistor, a third transistor, and a resistance element is provided. The first transistor includes a first gate and is coupled between a first electrode and a second electrode. The second transistor includes a second gate, a third electrode, and a fourth electrode. The second gate is coupled to the second electrode. The third electrode is coupled to a control electrode. The third transistor includes a third gate, a fifth electrode, and a sixth electrode. The third gate is coupled to the control electrode. The fifth electrode is coupled to the fourth electrode. The sixth electrode is coupled to the second electrode. The resistance element is coupled between the third electrode and the first gate.Type: GrantFiled: November 16, 2021Date of Patent: August 15, 2023Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Jian-Hsing Lee, Yeh-Jen Huang, Li-Yang Hong, Hwa-Chyi Chiou
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Publication number: 20230155375Abstract: An electronic device including a first transistor, a second transistor, a third transistor, and a resistance element is provided. The first transistor includes a first gate and is coupled between a first electrode and a second electrode. The second transistor includes a second gate, a third electrode, and a fourth electrode. The second gate is coupled to the second electrode. The third electrode is coupled to a control electrode. The third transistor includes a third gate, a fifth electrode, and a sixth electrode. The third gate is coupled to the control electrode. The fifth electrode is coupled to the fourth electrode. The sixth electrode is coupled to the second electrode. The resistance element is coupled between the third electrode and the first gate.Type: ApplicationFiled: November 16, 2021Publication date: May 18, 2023Applicant: Vanguard International Semiconductor CorporationInventors: Jian-Hsing LEE, Yeh-Jen HUANG, Li-Yang HONG, Hwa-Chyi CHIOU
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Patent number: 11631663Abstract: A control circuit applied in a specific element and including a first transistor and an electrostatic discharge (ESD) protection circuit is provided. The specific element has a III-V semiconductor material and includes a control electrode, a first electrode and a second electrode. The first transistor is coupled between the first electrode and the second electrode and has the III-V semiconductor material. The ESD protection circuit is coupled to the control electrode, the first transistor and the second electrode. In response to an ESD event, the ESD protection circuit provides a discharge path to release the ESD current from the control electrode to the second electrode.Type: GrantFiled: April 23, 2020Date of Patent: April 18, 2023Assignee: Vanguard International Semiconductor CorporationInventors: Jian-Hsing Lee, Yeh-Jen Huang, Wen-Hsin Lin, Chun-Jung Chiu, Hwa-Chyi Chiou
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Publication number: 20220415828Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first drain conductive element of the source protective circuit partially overlaps a first source conductive element of the drain protective circuit.Type: ApplicationFiled: August 29, 2022Publication date: December 29, 2022Applicant: Vanguard International Semiconductor CorporationInventors: Jian-Hsing LEE, Shao-Chang HUANG, Chih-Hsuan LIN, Yu-Kai WANG, Karuna NIDHI, Hwa-Chyi CHIOU
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Patent number: 11527607Abstract: A semiconductor device includes at least one transistor, a shallow well region, a guard ring, and a plurality of first and second doped regions. The transistor is on a substrate and includes a source structure, a gate structure, and a drain structure. The shallow well region surrounds the transistor. The shallow well region has a first conductivity type. The guard ring surrounds the shallow well region. The guard ring has the first conductivity type. The first and second doped regions are disposed on the guard ring and surround the well region. The first doped regions and the second doped regions are alternately arranged in a shape of a loop. Each of the first doped regions and each of the second doped regions have opposite conductivity types.Type: GrantFiled: December 14, 2020Date of Patent: December 13, 2022Assignee: Vanguard International Semiconductor CorporationInventors: Karuna Nidhi, Chih-Hsuan Lin, Jian-Hsing Lee, Hwa-Chyi Chiou
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Patent number: 11527884Abstract: A protection circuit including a detection circuit, a current discharge element, a first transistor, and a second transistor is provided. The detection circuit is coupled between a first pad and a second pad to detect ESD events. In response to an ESD event, the detection circuit sets the detection signal to a predetermined level. The current discharge element is coupled between the first and second pads. In response to the detection signal being at the predetermined level, the current discharge element is turned on so that the ESD current passes through the current discharge element. The first transistor is coupled between a core circuit and the second pad. The second transistor is coupled between the first transistor and the second pad. In response to the detection signal being at the predetermined level, the second transistor is turned on to turn off the first transistor.Type: GrantFiled: March 8, 2021Date of Patent: December 13, 2022Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Hsuan Lin, Shao-Chang Huang, Yeh-Ning Jou, Hwa-Chyi Chiou, Ching-Ho Li
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Patent number: 11476207Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first drain conductive element of the source protective circuit partially overlaps a first source conductive element of the drain protective circuit.Type: GrantFiled: October 23, 2019Date of Patent: October 18, 2022Assignee: Vanguard International Semiconductor CorporationInventors: Jian-Hsing Lee, Shao-Chang Huang, Chih-Hsuan Lin, Yu-Kai Wang, Karuna Nidhi, Hwa-Chyi Chiou
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Publication number: 20220285932Abstract: A protection circuit including a detection circuit, a current discharge element, a first transistor, and a second transistor is provided. The detection circuit is coupled between a first pad and a second pad to detect ESD events. In response to an ESD event, the detection circuit sets the detection signal to a predetermined level. The current discharge element is coupled between the first and second pads. In response to the detection signal being at the predetermined level, the current discharge element is turned on so that the ESD current passes through the current discharge element. The first transistor is coupled between a core circuit and the second pad. The second transistor is coupled between the first transistor and the second pad. In response to the detection signal being at the predetermined level, the second transistor is turned on to turn off the first transistor.Type: ApplicationFiled: March 8, 2021Publication date: September 8, 2022Applicant: Vanguard International Semiconductor CorporationInventors: Chih-Hsuan LIN, Shao-Chang HUANG, Yeh-Ning JOU, Hwa-Chyi CHIOU, Ching-Ho LI
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Publication number: 20220190106Abstract: A semiconductor device includes at least one transistor, a shallow well region, a guard ring, and a plurality of first and second doped regions. The transistor is on a substrate and includes a source structure, a gate structure, and a drain structure. The shallow well region surrounds the transistor. The shallow well region has a first conductivity type. The guard ring surrounds the shallow well region. The guard ring has the first conductivity type. The first and second doped regions are disposed on the guard ring and surround the well region. The first doped regions and the second doped regions are alternately arranged in a shape of a loop. Each of the first doped regions and each of the second doped regions have opposite conductivity types.Type: ApplicationFiled: December 14, 2020Publication date: June 16, 2022Applicant: Vanguard International Semiconductor CorporationInventors: Karuna NIDHI, Chih-Hsuan LIN, Jian-Hsing LEE, Hwa-Chyi CHIOU
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Patent number: 11196249Abstract: An electrostatic discharge (ESD) blocking circuit including an internal circuit, a first Schottky diode, and an ESD releasing element is provided. The first Schottky diode is coupled between a specific node and the internal circuit. The ESD releasing element is coupled between the specific node and the first power terminal. In response to an ESD event occurring at the specific node, the ESD releasing element is turned on to release the ESD current from the specific node to the first power terminal.Type: GrantFiled: April 21, 2020Date of Patent: December 7, 2021Assignee: Vanguard International Semiconductor CorporationInventors: Yeh-Ning Jou, Jian-Hsing Lee, Shao-Chang Huang, Chih-Hsuan Lin, Hwa-Chyi Chiou
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Publication number: 20210335771Abstract: A control circuit applied in a specific element and including a first transistor and an electrostatic discharge (ESD) protection circuit is provided. The specific element has a III-V semiconductor material and includes a control electrode, a first electrode and a second electrode. The first transistor is coupled between the first electrode and the second electrode and has the III-V semiconductor material. The ESD protection circuit is coupled to the control electrode, the first transistor and the second electrode. In response to an ESD event, the ESD protection circuit provides a discharge path to release the ESD current from the control electrode to the second electrode.Type: ApplicationFiled: April 23, 2020Publication date: October 28, 2021Applicant: Vanguard International Semiconductor CorporationInventors: Jian-Hsing LEE, Yeh-Jen HUANG, Wen-Hsin LIN, Chun-Jung CHIU, Hwa-Chyi CHIOU
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Publication number: 20210328425Abstract: An electrostatic discharge (ESD) blocking circuit including an internal circuit, a first Schottky diode, and an ESD releasing element is provided. The first Schottky diode is coupled between a specific node and the internal circuit. The ESD releasing element is coupled between the specific node and the first power terminal. In response to an ESD event occurring at the specific node, the ESD releasing element is turned on to release the ESD current from the specific node to the first power terminal.Type: ApplicationFiled: April 21, 2020Publication date: October 21, 2021Applicant: Vanguard International Semiconductor CorporationInventors: Yeh-Ning JOU, Jian-Hsing LEE, Shao-Chang HUANG, Chih-Hsuan LIN, Hwa-Chyi CHIOU
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Patent number: 11043486Abstract: A semiconductor structure includes a first P-well, a first P-type diffusion region, a first N-type diffusion region, a second P-type diffusion region, and a first poly-silicon layer. The first P-type diffusion region is deposited in the first P-well and coupled to a first electrode. The first N-well is adjacent to the P-well. The first N-type diffusion region is deposited in the first N-well. The second P-type diffusion region is deposited between the first P-type diffusion region and the first N-type diffusion region, which is deposited in the first N-well. The second P-type diffusion region and the first N-type diffusion region are coupled to a second electrode. The first poly-silicon layer is deposited on the first P-type diffusion region.Type: GrantFiled: November 7, 2018Date of Patent: June 22, 2021Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Hsuan Lin, Shao-Chang Huang, Jia-Rong Yeh, Yeh-Ning Jou, Hwa-Chyi Chiou
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Publication number: 20210125943Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate disposed on the semiconductor substrate. The semiconductor device structure also includes a source doped region and a drain doped region on two opposite sides of the gate. The semiconductor device structure further includes a source protective circuit and a drain protective circuit. From a side perspective view, a first drain conductive element of the source protective circuit partially overlaps a first source conductive element of the drain protective circuit.Type: ApplicationFiled: October 23, 2019Publication date: April 29, 2021Applicant: Vanguard International Semiconductor CorporationInventors: Jian-Hsing LEE, Shao-Chang HUANG, Chih-Hsuan LIN, Yu-Kai WANG, Karuna NIDHI, Hwa-Chyi CHIOU
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Patent number: 10867989Abstract: A driving circuit including a detection circuit, a first control circuit, a second control circuit, and a driving transistor is provided. The detection circuit is coupled between a first power terminal and a second power terminal and generates a detection signal according to the voltages of the first and second power terminals. The first control circuit generates a first control signal according to the detection signal. The second control circuit generates a second control signal according to the detection signal. The driving transistor is coupled between an input-output pad and the second power terminal. When the detection signal is at a first level, the driving transistor is turned on according to the first control signal. When the detection signal is at a second level, the driving transistor is configured to operate according to the second control signal. The first level is different from the second level.Type: GrantFiled: July 30, 2018Date of Patent: December 15, 2020Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Chih-Hsuan Lin, Shao-Chang Huang, Chun-Chih Chen, Hwa-Chyi Chiou