Patents by Inventor Hwal Pyo Kim

Hwal Pyo Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220246641
    Abstract: A semiconductor device includes: a stack structure including insulating layers and conductive layers, which are alternately stacked; a channel structure penetrating the stack structure; data storage patterns respectively interposed between the conductive layers and the channel structure; blocking patterns respectively interposed between the conductive layers and the data storage patterns; insulating patterns respectively interposed between the insulating layers and the channel structure; and insulative liners interposed between the insulating layers and the insulating patterns, the insulative liners respectively surrounding the insulating patterns.
    Type: Application
    Filed: April 14, 2022
    Publication date: August 4, 2022
    Applicant: SK hynix Inc.
    Inventors: Ki Hong LEE, Hwal Pyo KIM, Seung Woo HAN
  • Patent number: 11362104
    Abstract: A semiconductor memory device includes a substrate including a peripheral circuit, a stepped dummy stack overlapping the substrate and including a plurality of steps extending in a first direction, a plurality of contact groups passing through the stepped dummy stack, and upper lines respectively connected to the contact groups. The contact groups include a first contact group having two or more first contact plugs arranged in the first direction. The upper lines include a first upper line commonly connected to the first contact plugs.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: June 14, 2022
    Assignee: SK hynix Inc.
    Inventors: Byung Woo Kang, Min Sung Ko, Gwang Been Kim, Hwal Pyo Kim, Jin Taek Park, Young Ock Hong
  • Patent number: 11309330
    Abstract: A semiconductor device includes: a stack structure including insulating layers and conductive layers, which are alternately stacked; a channel structure penetrating the stack structure; data storage patterns respectively interposed between the conductive layers and the channel structure; blocking patterns respectively interposed between the conductive layers and the data storage patterns; insulating patterns respectively interposed between the insulating layers and the channel structure; and insulative liners interposed between the insulating layers and the insulating patterns, the insulative liners respectively surrounding the insulating patterns.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: April 19, 2022
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Hwal Pyo Kim, Seung Woo Han
  • Publication number: 20210265381
    Abstract: A semiconductor device includes: a stack structure including insulating layers and conductive layers, which are alternately stacked; a channel structure penetrating the stack structure; data storage patterns respectively interposed between the conductive layers and the channel structure; blocking patterns respectively interposed between the conductive layers and the data storage patterns; insulating patterns respectively interposed between the insulating layers and the channel structure; and insulative liners interposed between the insulating layers and the insulating patterns, the insulative liners respectively surrounding the insulating patterns.
    Type: Application
    Filed: July 29, 2020
    Publication date: August 26, 2021
    Applicant: SK hynix Inc.
    Inventors: Ki Hong LEE, Hwal Pyo KIM, Seung Woo HAN
  • Publication number: 20210134823
    Abstract: A semiconductor memory device includes a substrate including a peripheral circuit, a stepped dummy stack overlapping the substrate and including a plurality of steps extending in a first direction, a plurality of contact groups passing through the stepped dummy stack, and upper lines respectively connected to the contact groups. The contact groups include a first contact group having two or more first contact plugs arranged in the first direction. The upper lines include a first upper line commonly connected to the first contact plugs.
    Type: Application
    Filed: June 30, 2020
    Publication date: May 6, 2021
    Applicant: SK hynix Inc.
    Inventors: Byung Woo KANG, Min Sung KO, Gwang Been KIM, Hwal Pyo KIM, Jin Taek PARK, Young Ock HONG
  • Publication number: 20210091109
    Abstract: A semiconductor device includes: a stack structure including a cell region and a contact region; a channel structure penetrating the cell region of the stack structure; trenches penetrating the contact region of the stack structure to different depths; and a stop structure penetrating the contact region of the stack structure, the stop structure being located between the trenches.
    Type: Application
    Filed: May 11, 2020
    Publication date: March 25, 2021
    Applicant: SK hynix Inc.
    Inventors: Byung Woo KANG, Sae Jun KWON, Seung Min LEE, Hwal Pyo KIM, Jin Taek PARK, Seung Woo HAN, Young Ock HONG
  • Publication number: 20210057431
    Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure including trenches having different depths, forming an insulating layer on the stacked structure to fill the trenches, and forming a plurality of protrusions located corresponding to locations of the trenches by patterning the insulating layer. The method also includes forming insulating patterns filling the trenches, respectively, by planarizing the patterned insulating layer including the plurality of protrusions.
    Type: Application
    Filed: April 16, 2020
    Publication date: February 25, 2021
    Applicant: SK hynix Inc.
    Inventors: Byung Woo KANG, Sae Jun KWON, Hwal Pyo KIM, Jin Taek PARK, Yang Seok LIM, Young Ock HONG
  • Patent number: 7121933
    Abstract: Disclosed is a chemical mechanical polishing apparatus for polishing a surface of a wafer using a mechanical friction as well as a chemical polishing agent. The chemical mechanical polishing apparatus includes a polishing head for absorbing a wafer and a polishing means for polishing the wafer. The polishing apparatus may include a platen composed of at least three segments formed in conformity with polishing zones, a polishing pad provided on each of the segments, and a support for supporting the segments such that the segments are separately adjustable in the height depending on the polishing zones and are rotatable.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: October 17, 2006
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Hwal Pyo Kim