Patents by Inventor Hwal Pyo Kim
Hwal Pyo Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11770931Abstract: A semiconductor device includes: a stack structure including insulating layers and conductive layers, which are alternately stacked; a channel structure penetrating the stack structure; data storage patterns respectively interposed between the conductive layers and the channel structure; blocking patterns respectively interposed between the conductive layers and the data storage patterns; insulating patterns respectively interposed between the insulating layers and the channel structure; and insulative liners interposed between the insulating layers and the insulating patterns, the insulative liners respectively surrounding the insulating patterns.Type: GrantFiled: April 14, 2022Date of Patent: September 26, 2023Assignee: SK hynix Inc.Inventors: Ki Hong Lee, Hwal Pyo Kim, Seung Woo Han
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Patent number: 11587941Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure including trenches having different depths, forming an insulating layer on the stacked structure to fill the trenches, and forming a plurality of protrusions located corresponding to locations of the trenches by patterning the insulating layer. The method also includes forming insulating patterns filling the trenches, respectively, by planarizing the patterned insulating layer including the plurality of protrusions.Type: GrantFiled: April 16, 2020Date of Patent: February 21, 2023Assignee: SK hynix Inc.Inventors: Byung Woo Kang, Sae Jun Kwon, Hwal Pyo Kim, Jin Taek Park, Yang Seok Lim, Young Ock Hong
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Patent number: 11574920Abstract: A semiconductor device includes: a stack structure including a cell region and a contact region; a channel structure penetrating the cell region of the stack structure; trenches penetrating the contact region of the stack structure to different depths; and a stop structure penetrating the contact region of the stack structure, the stop structure being located between the trenches.Type: GrantFiled: May 11, 2020Date of Patent: February 7, 2023Assignee: SK hynix Inc.Inventors: Byung Woo Kang, Sae Jun Kwon, Seung Min Lee, Hwal Pyo Kim, Jin Taek Park, Seung Woo Han, Young Ock Hong
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Publication number: 20220246641Abstract: A semiconductor device includes: a stack structure including insulating layers and conductive layers, which are alternately stacked; a channel structure penetrating the stack structure; data storage patterns respectively interposed between the conductive layers and the channel structure; blocking patterns respectively interposed between the conductive layers and the data storage patterns; insulating patterns respectively interposed between the insulating layers and the channel structure; and insulative liners interposed between the insulating layers and the insulating patterns, the insulative liners respectively surrounding the insulating patterns.Type: ApplicationFiled: April 14, 2022Publication date: August 4, 2022Applicant: SK hynix Inc.Inventors: Ki Hong LEE, Hwal Pyo KIM, Seung Woo HAN
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Patent number: 11362104Abstract: A semiconductor memory device includes a substrate including a peripheral circuit, a stepped dummy stack overlapping the substrate and including a plurality of steps extending in a first direction, a plurality of contact groups passing through the stepped dummy stack, and upper lines respectively connected to the contact groups. The contact groups include a first contact group having two or more first contact plugs arranged in the first direction. The upper lines include a first upper line commonly connected to the first contact plugs.Type: GrantFiled: June 30, 2020Date of Patent: June 14, 2022Assignee: SK hynix Inc.Inventors: Byung Woo Kang, Min Sung Ko, Gwang Been Kim, Hwal Pyo Kim, Jin Taek Park, Young Ock Hong
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Patent number: 11309330Abstract: A semiconductor device includes: a stack structure including insulating layers and conductive layers, which are alternately stacked; a channel structure penetrating the stack structure; data storage patterns respectively interposed between the conductive layers and the channel structure; blocking patterns respectively interposed between the conductive layers and the data storage patterns; insulating patterns respectively interposed between the insulating layers and the channel structure; and insulative liners interposed between the insulating layers and the insulating patterns, the insulative liners respectively surrounding the insulating patterns.Type: GrantFiled: July 29, 2020Date of Patent: April 19, 2022Assignee: SK hynix Inc.Inventors: Ki Hong Lee, Hwal Pyo Kim, Seung Woo Han
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Publication number: 20210265381Abstract: A semiconductor device includes: a stack structure including insulating layers and conductive layers, which are alternately stacked; a channel structure penetrating the stack structure; data storage patterns respectively interposed between the conductive layers and the channel structure; blocking patterns respectively interposed between the conductive layers and the data storage patterns; insulating patterns respectively interposed between the insulating layers and the channel structure; and insulative liners interposed between the insulating layers and the insulating patterns, the insulative liners respectively surrounding the insulating patterns.Type: ApplicationFiled: July 29, 2020Publication date: August 26, 2021Applicant: SK hynix Inc.Inventors: Ki Hong LEE, Hwal Pyo KIM, Seung Woo HAN
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Publication number: 20210134823Abstract: A semiconductor memory device includes a substrate including a peripheral circuit, a stepped dummy stack overlapping the substrate and including a plurality of steps extending in a first direction, a plurality of contact groups passing through the stepped dummy stack, and upper lines respectively connected to the contact groups. The contact groups include a first contact group having two or more first contact plugs arranged in the first direction. The upper lines include a first upper line commonly connected to the first contact plugs.Type: ApplicationFiled: June 30, 2020Publication date: May 6, 2021Applicant: SK hynix Inc.Inventors: Byung Woo KANG, Min Sung KO, Gwang Been KIM, Hwal Pyo KIM, Jin Taek PARK, Young Ock HONG
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Publication number: 20210091109Abstract: A semiconductor device includes: a stack structure including a cell region and a contact region; a channel structure penetrating the cell region of the stack structure; trenches penetrating the contact region of the stack structure to different depths; and a stop structure penetrating the contact region of the stack structure, the stop structure being located between the trenches.Type: ApplicationFiled: May 11, 2020Publication date: March 25, 2021Applicant: SK hynix Inc.Inventors: Byung Woo KANG, Sae Jun KWON, Seung Min LEE, Hwal Pyo KIM, Jin Taek PARK, Seung Woo HAN, Young Ock HONG
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Publication number: 20210057431Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure including trenches having different depths, forming an insulating layer on the stacked structure to fill the trenches, and forming a plurality of protrusions located corresponding to locations of the trenches by patterning the insulating layer. The method also includes forming insulating patterns filling the trenches, respectively, by planarizing the patterned insulating layer including the plurality of protrusions.Type: ApplicationFiled: April 16, 2020Publication date: February 25, 2021Applicant: SK hynix Inc.Inventors: Byung Woo KANG, Sae Jun KWON, Hwal Pyo KIM, Jin Taek PARK, Yang Seok LIM, Young Ock HONG
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Patent number: 7121933Abstract: Disclosed is a chemical mechanical polishing apparatus for polishing a surface of a wafer using a mechanical friction as well as a chemical polishing agent. The chemical mechanical polishing apparatus includes a polishing head for absorbing a wafer and a polishing means for polishing the wafer. The polishing apparatus may include a platen composed of at least three segments formed in conformity with polishing zones, a polishing pad provided on each of the segments, and a support for supporting the segments such that the segments are separately adjustable in the height depending on the polishing zones and are rotatable.Type: GrantFiled: November 24, 2004Date of Patent: October 17, 2006Assignee: Dongbu Electronics Co., Ltd.Inventor: Hwal Pyo Kim