Patents by Inventor Hyo Sub YEOM

Hyo Sub YEOM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088021
    Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers, which are stacked in an alternating manner; at least one support structure penetrating the stack structure in a substantially vertical manner, the at least one support structure being formed in a contact region; and a contact plug penetrating the stack structure in a substantially vertical manner, the contact plug being formed in the contact region, the contact plug being connected to a contact pad that is disposed on the bottom of the stack structure. The at least one support structure is formed of an oxide layer.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Applicant: SK hynix Inc.
    Inventors: Jae Yoon NOH, Tae Kyung KIM, Hyo Sub YEOM, Jeong Yun LEE
  • Patent number: 11923247
    Abstract: There may be presented a method of manufacturing a semiconductor chip. A first layer stack in which first material layers and second material layers are alternately stacked is formed over a semiconductor substrate including a chip region and a scribe lane region, and first crack propagation guides are formed on the first layer stack. A second layer stack is formed on the first layer stack and the first crack propagation guides, and second crack propagation guides are formed. A semiconductor chip is separated from the semiconductor substrate.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: March 5, 2024
    Assignee: SK hynix Inc.
    Inventor: Hyo Sub Yeom
  • Patent number: 11901284
    Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers, which are stacked in an alternating manner; at least one support structure penetrating the stack structure in a substantially vertical manner, the at least one support structure being formed in a contact region; and a contact plug penetrating the stack structure in a substantially vertical manner, the contact plug being formed in the contact region, the contact plug being connected to a contact pad that is disposed on the bottom of the stack structure. The at least one support structure is formed of an oxide layer.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: February 13, 2024
    Assignee: SK hynix Inc.
    Inventors: Jae Yoon Noh, Tae Kyung Kim, Hyo Sub Yeom, Jeong Yun Lee
  • Patent number: 11862555
    Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers, which are stacked in an alternating manner; at least one support structure penetrating the stack structure in a substantially vertical manner, the at least one support structure being formed in a contact region; and a contact plug penetrating the stack structure in a substantially vertical manner, the contact plug being formed in the contact region, the contact plug being connected to a contact pad that is disposed on the bottom of the stack structure. The at least one support structure is formed of an oxide layer.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: January 2, 2024
    Assignee: SK hynix Inc.
    Inventors: Jae Yoon Noh, Tae Kyung Kim, Hyo Sub Yeom, Jeong Yun Lee
  • Publication number: 20230328983
    Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor memory device includes a first source structure and a second source structure spaced apart from each other over a semiconductor substrate, a filling pattern between the first source structure and the second source structure, a memory cell array overlapping with the first source structure, and a discharge contact penetrating the second source structure and connected to the semiconductor substrate.
    Type: Application
    Filed: October 5, 2022
    Publication date: October 12, 2023
    Applicant: SK hynix Inc.
    Inventor: Hyo Sub YEOM
  • Publication number: 20230021440
    Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor memory device includes a metal pattern including a first line part extending in a first direction and a second line part which is connected to the first line part and extends in a second direction to intersect with the first line part, and a source structure which has a trench. The metal pattern is formed in the trench and the source structure is in contact with a sidewall of the metal pattern.
    Type: Application
    Filed: December 16, 2021
    Publication date: January 26, 2023
    Applicant: SK hynix Inc.
    Inventors: Hyo Sub YEOM, Seung Ju OH
  • Publication number: 20220367506
    Abstract: A semiconductor memory device includes a semiconductor substrate including an upper surface extending in a horizontal direction, a source structure including a trench extending in the horizontal direction, the source structure disposed above the semiconductor substrate, a metal structure in the trench of the source structure and connecting the source structure to the semiconductor substrate, and memory cell strings disposed on both sides of the trench and connected to the source structure.
    Type: Application
    Filed: October 26, 2021
    Publication date: November 17, 2022
    Applicant: SK hynix Inc.
    Inventor: Hyo Sub YEOM
  • Publication number: 20220352023
    Abstract: There may be presented a method of manufacturing a semiconductor chip. A first layer stack in which first material layers and second material layers are alternately stacked is formed over a semiconductor substrate including a chip region and a scribe lane region, and first crack propagation guides are formed on the first layer stack. A second layer stack is formed on the first layer stack and the first crack propagation guides, and second crack propagation guides are formed. A semiconductor chip is separated from the semiconductor substrate.
    Type: Application
    Filed: September 8, 2021
    Publication date: November 3, 2022
    Applicant: SK hynix Inc.
    Inventor: Hyo Sub YEOM
  • Publication number: 20210090994
    Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers, which are stacked in an alternating manner; at least one support structure penetrating the stack structure in a substantially vertical manner, the at least one support structure being formed in a contact region; and a contact plug penetrating the stack structure in a substantially vertical manner, the contact plug being formed in the contact region, the contact plug being connected to a contact pad that is disposed on the bottom of the stack structure. The at least one support structure is formed of an oxide layer.
    Type: Application
    Filed: May 1, 2020
    Publication date: March 25, 2021
    Applicant: SK hynix Inc.
    Inventors: Jae Yoon NOH, Tae Kyung KIM, Hyo Sub YEOM, Jeong Yun LEE