Patents by Inventor HYOUNG-YOL MUN

HYOUNG-YOL MUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11887840
    Abstract: A semiconductor device includes a substrate. A conductive layer is disposed on the substrate and extends in a first direction. An insulating layer is disposed on the conductive layer and exposes at least a portion of the conductive layer through a via hole. The via hole includes a first face extending in a first slope relative to a top face of the conductive layer. A second face extends in a second slope relative to the top face of the conductive layer that is less than the first slope. A redistribution conductive layer includes a first pad area disposed in the via hole. A line area at least partially extends along the first face and the second face. The first face directly contacts the conductive layer. The second face is positioned at a higher level than the first face in a second direction perpendicular to a top face of the substrate.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: January 30, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min Sung Kang, Hyoung Yol Mun, Jun U Jin, Bo Hyun Kim, Sung Dong Cho, Won Hee Cho
  • Publication number: 20230016186
    Abstract: A semiconductor device includes a substrate. A conductive layer is disposed on the substrate and extends in a first direction. An insulating layer is disposed on the conductive layer and exposes at least a portion of the conductive layer through a via hole. The via hole includes a first face extending in a first slope relative to a top face of the conductive layer. A second face extends in a second slope relative to the top face of the conductive layer that is less than the first slope. A redistribution conductive layer includes a first pad area disposed in the via hole. A line area at least partially extends along the first face and the second face. The first face directly contacts the conductive layer. The second face is positioned at a higher level than the first face in a second direction perpendicular to a top face of the substrate.
    Type: Application
    Filed: February 23, 2022
    Publication date: January 19, 2023
    Inventors: Min Sung KANG, Hyoung Yol MUN, Jun U JIN, Bo Hyun KIM, Sung Dong CHO, Won Hee CHO
  • Patent number: 9437554
    Abstract: Provided is a semiconductor device. A semiconductor chip is disposed on a substrate. A first magnetic substance, a second magnetic substance and a third magnetic substance which are spaced apart from one another are formed on the semiconductor chip. The first magnetic substance and the second magnetic substance can be adjacent an edge of the semiconductor chip. The third magnetic substance can be adjacent a center of the semiconductor chip. The third magnetic substance is between the first magnetic substance and the second magnetic substance.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: September 6, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wook Ji, Hyoung-Yol Mun, Yeong-Lyeol Park, In-Kyum Lee
  • Patent number: 9293415
    Abstract: Semiconductor devices including a protection pattern for reducing galvanic corrosion and methods of forming the semiconductor devices are provided. The semiconductor devices may include a substrate including a keep out zone (KOZ) and a plurality of interconnections, which may be disposed outside of the KOZ on the substrate. The semiconductor devices may also include a through silicon via (TSV) in the KOZ. The TSV may pass through the substrate. The semiconductor device may further include a protection pattern, which may be electrically insulated from the TSV, may be disposed in the KOZ and may include a different conductive material from the TSV. A lower end of the protection pattern may be disposed at a level higher than a lower end of the TSV.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: March 22, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Ji Kim, Sung-Dong Cho, Hyoung-Yol Mun, Yeong-Lyeol Park, Seung-Taek Lee
  • Publication number: 20150340314
    Abstract: Semiconductor devices including a protection pattern for reducing galvanic corrosion and methods of forming the semiconductor devices are provided. The semiconductor devices may include a substrate including a keep out zone (KOZ) and a plurality of interconnections, which may be disposed outside of the KOZ on the substrate. The semiconductor devices may also include a through silicon via (TSV) in the KOZ. The TSV may pass through the substrate. The semiconductor device may further include a protection pattern, which may be electrically insulated from the TSV, may be disposed in the KOZ and may include a different conductive material from the TSV. A lower end of the protection pattern may be disposed at a level higher than a lower end of the TSV.
    Type: Application
    Filed: May 11, 2015
    Publication date: November 26, 2015
    Inventors: Eun-Ji KIM, Sung-Dong CHO, Hyoung-Yol MUN, Yeong-Lyeol PARK, Seung-Taek LEE
  • Patent number: 9087885
    Abstract: Provided is a method of fabricating a semiconductor device. In one embodiment, the method includes forming at least one unit device in a substrate and on a front side of the substrate, forming a through-silicon via (TSV) structure apart from the at least one unit device to substantially vertically penetrate the substrate, the TSV structure having a back end including a concave portion, forming an internal circuit on the front side of the substrate and a front end of the TSV structure to be electrically connected to the at least one unit device and the front end of the TSV structure, forming a front side bump on the front side of the substrate to be electrically connected to the front end of the TSV structure, forming a redistribution layer on a back side of the substrate to be electrically connected to the back end of the TSV structure, and forming a back side bump to be electrically connected to the redistribution layer.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: July 21, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Wook Ji, Yeong-Lyeol Park, Hyoung-Yol Mun, In-Kyum Lee
  • Patent number: 9070729
    Abstract: A wafer processing method, by which a device wafer may be aligned and bonded to a carrier wafer to perform a back grinding process for the device wafer and may be separated from the carrier wafer after performing the back grinding process, and a method of manufacturing a semiconductor device by using the wafer processing method are provided. The wafer processing method includes: disposing a first magnetic material on a front side of a wafer and disposing a second magnetic material on a carrier wafer, wherein a surface of the first magnetic material and a surface of the second magnetic material, which face each other, have opposite polarities; aligning and bonding the wafer to the carrier wafer by magnetic attraction between the first magnetic material and the second magnetic material; grinding a back side of the wafer to make the wafer thin; and separating the wafer from the carrier wafer.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: June 30, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-wook Ji, Hyoung-yol Mun, Yeong-Iyeol Park, Tae-je Cho
  • Publication number: 20150130075
    Abstract: Provided is a semiconductor device. A semiconductor chip is disposed on a substrate. A first magnetic substance, a second magnetic substance and a third magnetic substance which are spaced apart from one another are formed on the semiconductor chip. The first magnetic substance and the second magnetic substance can be adjacent an edge of the semiconductor chip. The third magnetic substance can be adjacent a center of the semiconductor chip. The third magnetic substance is between the first magnetic substance and the second magnetic substance.
    Type: Application
    Filed: July 14, 2014
    Publication date: May 14, 2015
    Inventors: Sang-Wook Ji, Hyoung-Yol Mun, Yeong-Lyeol Park, In-Kyum Lee
  • Publication number: 20150093880
    Abstract: A wafer processing method, by which a device wafer may be aligned and bonded to a carrier wafer to perform a back grinding process for the device wafer and may be separated from the carrier wafer after performing the back grinding process, and a method of manufacturing a semiconductor device by using the wafer processing method are provided. The wafer processing method includes: disposing a first magnetic material on a front side of a wafer and disposing a second magnetic material on a carrier wafer, wherein a surface of the first magnetic material and a surface of the second magnetic material, which face each other, have opposite polarities; aligning and bonding the wafer to the carrier wafer by magnetic attraction between the first magnetic material and the second magnetic material; grinding a back side of the wafer to make the wafer thin; and separating the wafer from the carrier wafer.
    Type: Application
    Filed: September 26, 2014
    Publication date: April 2, 2015
    Inventors: Sang-wook Ji, Hyoung-yol Mun, Yeong-Iyeol Park, Tae-je Cho
  • Publication number: 20150064899
    Abstract: Provided is a method of fabricating a semiconductor device. In one embodiment, the method includes forming at least one unit device in a substrate and on a front side of the substrate, forming a through-silicon via (TSV) structure apart from the at least one unit device to substantially vertically penetrate the substrate, the TSV structure having a back end including a concave portion, forming an internal circuit on the front side of the substrate and a front end of the TSV structure to be electrically connected to the at least one unit device and the front end of the TSV structure, forming a front side bump on the front side of the substrate to be electrically connected to the front end of the TSV structure, forming a redistribution layer on a back side of the substrate to be electrically connected to the back end of the TSV structure, and forming a back side bump to be electrically connected to the redistribution layer.
    Type: Application
    Filed: April 7, 2014
    Publication date: March 5, 2015
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: SANG-WOOK JI, YEONG-LYEOL PARK, HYOUNG-YOL MUN, IN-KYUM LEE