Abstract: In a method of correcting a design layout of a semiconductor device, misaligned values of a portion of points of a target pattern of each of a plurality of regions of interest in a semiconductor device fabricated based on an original layout are measured, misaligned values of unmeasured points of the target pattern are estimated by using an artificial neural network trained based on the measured misaligned values of the portion of points, and a target layout of the semiconductor device is generated by using the estimated misaligned values.

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a first keeper transistor that is connected to a first word line. The semiconductor memory device includes a second keeper transistor that is connected to a second word line. The first keeper transistor and the second keeper transistor have a merged channel. In some embodiments, the first keeper transistor and the second keeper transistor are in a sub-word line driver.

Abstract: The semiconductor memory device including a first sense amplifier region including first metal-oxide-semiconductor (MOS) transistors disposed in a well on a semiconductor substrate, a second sense amplifier region adjacent to the well and including second MOS transistors disposed on the semiconductor substrate, a guard band having a bar type structure and provided between the first MOS transistors in the well, and a guard ring partially or fully enclosing the second sense amplifier region in the semiconductor substrate may be provided.

Abstract: An integrated circuit memory device includes a substrate having a sense amplifier region or a word line driver region comprising circuits configured to operate a memory cell array. The substrate further includes a conjunction region adjacent the sense amplifier region or word line driver region and defining a boundary therebetween. A plurality of gate patterns extends on the substrate. The gate patterns include peripheral gate patterns extending in the sense amplifier region or word line driver region, and conjunction gate patterns extending in the conjunction region. Ones of the conjunction gate patterns and ones of the peripheral gate patterns proximate the boundary extend substantially parallel along the boundary between the conjunction region and the sense amplifier region or word line driver region.