Abstract: A method for generating and processing extended instructions and an apparatus using the method are provided. The method includes: transmitting, by a first device, a request packet according to an extended instruction that is generated based on a Gen-Z interface standard to a second device; and receiving, by the first device, a response packet including a result of performing the request packet from the second device. The extended instruction is generated based on a vendor-defined instruction set of the Gen-Z interface.

Abstract: A method for generating and processing extended instructions and an apparatus using the method are provided. The method includes: transmitting, by a first device, a request packet according to an extended instruction that is generated based on a Gen-Z interface standard to a second device; and receiving, by the first device, a response packet including a result of performing the request packet from the second device. The extended instruction is generated based on a vendor-defined instruction set of the Gen-Z interface.

Abstract: Disclosed are an optical input/output device and an opto-electronic system including the same. The device includes a bulk silicon substrate, at least one vertical-input light detection element monolithically integrated on a portion of the bulk silicon substrate, and at least one vertical-output light source element monolithically integrated on another portion of the bulk silicon substrate adjacent to the vertical-input light detection element. The vertical-output light source element includes a III-V compound semiconductor light source active layer combined with the bulk silicon substrate by a wafer bonding method.

Abstract: A memory interface apparatus is provided. The apparatus includes a central processing unit (CPU)-side protocol processor connected to a CPU through a parallel interface and a memory-side protocol processor connected to a memory through a parallel interface, and the CPU-side protocol processor and the memory-side protocol processor are connected through a serial link.

Abstract: Disclosed are an optical input/output device and an opto-electronic system including the same. The device includes a bulk silicon substrate, at least one vertical-input light detection element monolithically integrated on a portion of the bulk silicon substrate, and at least one vertical-output light source element monolithically integrated on another portion of the bulk silicon substrate adjacent to the vertical-input light detection element. The vertical-output light source element includes a III-V compound semiconductor light source active layer combined with the bulk silicon substrate by a wafer bonding method.

Abstract: A system for a multi-computer control according to an exemplary embodiment may include: an integrated process server to receive, from one or more computer terminals, display information including video data and terminal identification information through a physical layer transceiver, multiplex and serialize the received display information, transmit the multiplexed and serialized display information to a user process terminal, and transmit a received user input signal to a corresponding computer terminal; and the user process terminal to mix the display information and the multi-control interface, display, on a display device, the execution screens of the activated computer terminals, and transmit the user input signal to the integrated process server along with corresponding terminal identification information, wherein the display information is received from the integrated process server, and the user input signal is received from an input device.

Abstract: Disclosed are an optical input/output device and an opto-electronic system including the same. The device includes a bulk silicon substrate, at least one vertical-input light detection element monolithically integrated on a portion of the bulk silicon substrate, and at least one vertical-output light source element monolithically integrated on another portion of the bulk silicon substrate adjacent to the vertical-input light detection element. The vertical-output light source element includes a III-V compound semiconductor light source active layer combined with the bulk silicon substrate by a wafer bonding method.

Abstract: Disclosed are an optical input/output device and an opto-electronic system including the same. The device includes a bulk silicon substrate, at least one vertical-input light detection element monolithically integrated on a portion of the bulk silicon substrate, and at least one vertical-output light source element monolithically integrated on another portion of the bulk silicon substrate adjacent to the vertical-input light detection element. The vertical-output light source element includes a III-V compound semiconductor light source active layer combined with the bulk silicon substrate by a wafer bonding method.

Abstract: A memory interface apparatus is provided. The apparatus includes a central processing unit (CPU)-side protocol processor connected to a CPU through a parallel interface and a memory-side protocol processor connected to a memory through a parallel interface, and the CPU-side protocol processor and the memory-side protocol processor are connected through a serial link.

Abstract: Provided are a packet transmission and reception system, apparatus, and method. The packet transmission and reception system for distributing and transmitting data through a plurality of multi-lanes includes a first transmission and reception apparatus configured to include a plurality of first physical lanes and a plurality of first logical lanes connected to the plurality of first physical lanes, and a second transmission and reception apparatus configured to include a plurality of second physical lanes and a plurality of second logical lanes connected to the plurality of second physical lanes.

Abstract: Disclosed herein are a SATA host bus adapter using a optical signal and a method for connecting SATA storage using the optical signal. The SATA host bus adapter includes: a first conversion unit for converting a PCI-Express signal, transmitted from a host computer, into a data signal, using a protocol defined in a bus; a optical signal conversion unit for converting the data signal into a optical signal and for transmitting the optical signal to a optical signal reception unit; and a second conversion unit for converting the optical signal, received by the optical signal reception unit, into the data signal, for converting the data signal into a SATA signal, using the protocol, and for transmitting the SATA signal to the SATA storage.

Abstract: Disclosed are an optical input/output device and an opto-electronic system including the same. The device includes a bulk silicon substrate, at least one vertical-input light detection element monolithically integrated on a portion of the bulk silicon substrate, and at least one vertical-output light source element monolithically integrated on another portion of the bulk silicon substrate adjacent to the vertical-input light detection element. The vertical-output light source element includes a III-V compound semiconductor light source active layer combined with the bulk silicon substrate by a wafer bonding method.

Abstract: Disclosed herein are a SATA host bus adapter using a optical signal and a method for connecting SATA storage using the optical signal. The SATA host bus adapter includes: a first conversion unit for converting a PCI-Express signal, transmitted from a host computer, into a data signal, using a protocol defined in a bus; a optical signal conversion unit for converting the data signal into a optical signal and for transmitting the optical signal to a optical signal reception unit; and a second conversion unit for converting the optical signal, received by the optical signal reception unit, into the data signal, for converting the data signal into a SATA signal, using the protocol, and for transmitting the SATA signal to the SATA storage.

Abstract: A system for a multi-computer control according to an exemplary embodiment may include: an integrated process server to receive, from one or more computer terminals, display information including video data and terminal identification information through a physical layer transceiver, multiplex and serialize the received display information, transmit the multiplexed and serialized display information to a user process terminal, and transmit a received user input signal to a corresponding computer terminal; and the user process terminal to mix the display information and the multi-control interface, display, on a display device, the execution screens of the activated computer terminals, and transmit the user input signal to the integrated process server along with corresponding terminal identification information, wherein the display information is received from the integrated process server, and the user input signal is received from an input device.

Abstract: Disclosed are an apparatus and method for interfacing between a central processing unit (CPU) and a main memory unit, whereby a shared cache memory unit and the main memory unit are connected to each other using one optical signal transmission line. The apparatus for interfacing between the CPU and the main memory unit includes: a master optical connection protocol engine, converting operation control signals received from a shared cache memory unit of the CPU into serial signals; a first electrical-to-optical (E/O) converter, converting the serial signals converted by the master optical connection protocol engine into optical signals; a second E/O converter, converting the optical signals converted by the first E/O converter into serial signals; a slave optical connection protocol engine, converting the serial signals converted by the second E/O converter into operation control signals; and a memory controller having access to the main memory unit.

Abstract: Provided are a packet transmission and reception system, apparatus, and method. The packet transmission and reception system for distributing and transmitting data through a plurality of multi-lanes includes a first transmission and reception apparatus configured to include a plurality of first physical lanes and a plurality of first logical lanes connected to the plurality of first physical lanes, and a second transmission and reception apparatus configured to include a plurality of second physical lanes and a plurality of second logical lanes connected to the plurality of second physical lanes.

Abstract: Provided are a heterogeneous memory system and a data communication method in the same. The heterogeneous memory system includes a plurality of different kinds of memory cells, and a central processing unit (CPU) configured to communicate with each of the plurality of memory cells using a high-speed serial link technique. The CPU includes a CPU protocol engine that generates and packetizes command data to be transmitted to at least one of the plurality of memory cells, and each of the plurality of memory cells include a memory protocol engine configured to analyze the command data received from the CPU, and a memory controller configured to perform the corresponding operation according to the analysis result in the memory protocol engine.

Abstract: An interface circuit configured to transmit and receive signals between electronic devices is provided.

Abstract: Disclosed are an apparatus and method for interfacing between a central processing unit (CPU) and a main memory unit, whereby a shared cache memory unit and the main memory unit are connected to each other using one optical signal transmission line. The apparatus for interfacing between the CPU and the main memory unit includes: a master optical connection protocol engine, converting operation control signals received from a shared cache memory unit of the CPU into serial signals; a first electrical-to-optical (E/O) converter, converting the serial signals converted by the master optical connection protocol engine into optical signals; a second E/O converter, converting the optical signals converted by the first E/O converter into serial signals; a slave optical connection protocol engine, converting the serial signals converted by the second E/O converter into operation control signals; and a memory controller having access to the main memory unit.

Abstract: Disclosed are a double data rate synchronous dynamic random access memory module and a configuring method thereof. The DDR SDRAM module in accordance with an embodiment of the present invention includes: a plurality of memory chips; and a serial transceiver portion configured to serially receive first serial data including a control signal and data transferred from outside for the plurality of memory chips and to provide the control signal and the data included in the serially received first serial data to the plurality of memory chips.