Abstract: An image processing apparatus and a method thereof are provided. The image processing apparatus includes at least one processor configured to implement: a decoder which decodes input image data; and a rendering module which renders the decoded image data according to a rendering cycle which corresponds to a refresh rate of a display to display a plurality of image frames of the image data, wherein the decoder decodes the input image data only when the processor is not being in use for rendering by the rendering module.

Abstract: A memory device including first to fourth cell blocks, each including a plurality of normal columns and one or more redundancy columns and a control unit suitable for repairing the normal columns using the redundancy columns in the first and the second cell blocks using first repair information and repairing the normal columns using the redundancy columns in the third and the fourth cell blocks using second repair information when the memory device is set as a first mode, and suitable for repairing the normal columns using the redundancy columns in the first and the third cell blocks using the first repair information and repairing the normal columns using the redundancy columns in the second and the fourth cell blocks using the second repair information when the memory device is set as a second mode.

Abstract: A compound represented by Chemical Formula 1, an organic optoelectronic device including the same, and a display device including the organic optoelectronic device are provided. The structure of the compound represented by Chemical Formula 1 is described in the present specification.

Abstract: A latch circuit may include first to fourth storage nodes; first to fourth transistor pairs, each including a PMOS transistor and an NMOS transistor connected in series through a corresponding one of the first to fourth storage nodes, wherein each of the first to fourth storage nodes is connected to a gate of an NMOS transistor of a transistor pair in a previous stage and a gate of a PMOS transistor of a transistor pair in a next stage; a first connection unit suitable for connecting a data bus with a Kth storage node of the first to fourth storage nodes when read and write operations are performed, wherein K is an integer from 1 to 4; and second connection units suitable for connecting the data bus with one or more of the first to fourth storage nodes, except for the Kth storage node, when the write operation is performed.

Abstract: A latch circuit may include first to fourth storage nodes; first to fourth transistor pairs, each including a PMOS transistor and an NMOS transistor connected in series through a corresponding one of the first to fourth storage nodes, wherein each of the first to fourth storage nodes is connected to a gate of an NMOS transistor of a transistor pair in a previous stage and a gate of a PMOS transistor of a transistor pair in a next stage; a first connection unit suitable for connecting a data bus with a Kth storage node of the first to fourth storage nodes when read and write operations are performed, wherein K is an integer from 1 to 4; and second connection units suitable for connecting the data bus with one or more of the first to fourth storage nodes, except for the Kth storage node, when the write operation is performed.

Abstract: A compound for an organic optoelectronic device, an organic light-emitting device including the same, and a display device including the organic light-emitting device are disclosed, the compound for an organic optoelectronic device being represented by Chemical Formula 1,

Abstract: A system including a circuit integrated with a semiconductor is provided. The system includes a first data line, a second data line, and a first sense amp configured to sense and amplify data of the first data line. The first sense amp is also configured to transfer the amplified data to the second data line in response to a third control signal. The system also includes a control signal generation circuit configured to generate a first control signal for controlling a precharge of the first data line and a second control signal for controlling a reset of the second data line in response to a preparatory signal and a third control signal. The third control signal is generated in response to the first control signal and the second control signal.