Abstract: The present disclosure provides a dual cooling water heater including a main body on which a substrate is seated, a flow path forming part connected to the main body and having first and second flow paths provided on one surface thereof, a first heating element disposed on the other surface of the flow path forming part and configured to heat the first flow path, a second heating element disposed on the other surface of the flow path forming part and configured to heat the second flow path, and a control unit configured to control a temperature and a flow rate of cooling water moving through the first flow path and a temperature and a flow rate of cooling water moving through the second flow path by controlling a temperature of the first heating element and a temperature of the second heating element.

Abstract: The present disclosure includes cationic carrier units comprising (i) a water soluble polymer, (ii) a positively charged carrier, (iii) a hydrophobic moiety, and (iv) a crosslinking moeity, wherein when the cationic carrier unit is mixed with an anionic payload (e.g., an RNA and/or DNA) that electrostatically interacts with the cationic carrier unit, the resulting composition self-organizes into a micelle encapsulating the anionic payload in its core. The cationic carrier units can also comprise a tissue specific targeting moiety, which would be displayed on the surface of the micelle. The disclosure also includes micelles comprising the cationic carrier units of the disclosure, methods of manufacture of cationic carrier units and micelles, pharmaceutical compositions comprising the micelles, and also methods of treating diseases or conditions comprising administering the micelles to a subject in need thereof.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an element isolation layer, the element isolation layer defining an active region, a plurality of word lines traversing the active region in a first direction, and a plurality of bit line structures on the substrate and connected to the active region, the plurality of bit line structures extending in a second direction different from the first direction. Each of the plurality of bit line structures includes a ruthenium line wiring including a bottom surface and a top surface opposite to the bottom surface, a lower graphene layer in contact with the bottom surface of the ruthenium line wiring and extending along the bottom surface of the ruthenium line wiring, and a wiring line capping layer extending along the top surface of the ruthenium line wiring.

Abstract: A deposition apparatus includes an upper shower head and a lower shower head within a process chamber, the upper shower head and the lower shower head facing each other, a support structure between the upper shower head and the lower shower head, the support structure being connected to the lower shower head to support a wafer, and a plasma process region between the wafer supported by the support structure and the lower shower head, wherein the lower shower head includes lower holes to jet a lower gas in a direction of the wafer, wherein the upper shower head includes upper holes to jet an upper gas in a direction of the wafer, and wherein the support structure includes through opening portions to discharge a portion of the lower gas jetted through the lower holes to a space between the support structure and the upper shower head.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an element isolation layer, the element isolation layer defining an active region, a plurality of word lines traversing the active region in a first direction, and a plurality of bit line structures on the substrate and connected to the active region, the plurality of bit line structures extending in a second direction different from the first direction. Each of the plurality of bit line structures includes a ruthenium line wiring including a bottom surface and a top surface opposite to the bottom surface, a lower graphene layer in contact with the bottom surface of the ruthenium line wiring and extending along the bottom surface of the ruthenium line wiring, and a wiring line capping layer extending along the top surface of the ruthenium line wiring.

Abstract: An embodiment discloses a method of manufacturing a rare-earth magnet, the method including: preparing a magnetic sintered body including RE, Fe, and B as compositional components (RE is selected from one or two or more selected from rare earth elements); applying a solution containing a grain boundary diffusion material to the sintered body; and performing grain boundary diffusion by heat-treating the sintered body, wherein the grain boundary diffusion material includes a heavy rare earth element (HREE) hydride and a light rare earth element (LREE) hydride.

Abstract: A deposition apparatus for depositing a material on a wafer, the apparatus including a lower shower head; an upper shower head disposed on the lower shower head, the upper shower head facing the lower shower head; and a support structure between the upper shower head and the lower shower head, the wafer being supportable by the support structure, wherein the upper shower head includes upper holes for providing an upper gas onto the wafer, the lower shower head includes lower holes for providing a lower gas onto the wafer, the support structure includes a ring body surrounding the wafer; a plurality of ring support shafts between the ring body and the lower shower head; and a plurality of wafer supports extending inwardly from a lower region of the ring body to support the wafer, and the plurality of wafer supports are spaced apart from one another.

Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include a plurality of gate electrodes that are stacked on a substrate and are spaced apart from each other in a vertical direction and a channel region extending through the plurality of gate electrodes in the vertical direction. Each of the plurality of gate electrodes may include a first conductive layer defining a recess recessed toward the channel region, and a second conductive layer in the recess defined by the first conductive layer. A first concentration of impurities in the second conductive layer may be higher than a second concentration of the impurities in the first conductive layer, and the impurities may include nitrogen (N).

Abstract: A semiconductor memory device may include a substrate, gate electrode structures stacked on the substrate, insulation patterns between the gate electrode structures, vertical channels penetrating through the gate electrode structures and the insulation patterns, and a data storage pattern. The vertical channels may be electrically connected to the substrate. The data storage pattern may be arranged between the gate electrode structures and the vertical channels. Each of the gate electrode structures may include a barrier film, a metal gate, and a crystal grain boundary plugging layer. The crystal grain boundary plugging layer may be between the barrier film and the metal gate.

Abstract: A method of manufacturing a semiconductor device includes alternately stacking sacrificial layers and interlayer insulating layers on a substrate, to form a stack structure; forming channels penetrating through the stack structure; forming separation regions penetrating through the stack structure; forming lateral openings by removing the sacrificial layers through the separation regions; and forming gate electrodes in the lateral openings. Forming the gate electrodes may include forming a nucleation layer in the lateral openings by supplying a source gas and a first reaction gas, and forming a bulk layer on the nucleation layer to fill the lateral openings by supplying the source gas and a second reaction gas, different from the first reaction gas. The first reaction gas may be supplied from a first reaction gas source, stored in a gas charging unit, and supplied from the gas charging unit.

Abstract: A touch window according to one embodiment comprises: a substrate having an effective area and an ineffective area; a sensing electrode arranged in the effective area and sensing a position; and a wiring arranged in the effective area and the ineffective area and electrically connecting to the sensing electrode, wherein the wiring comprises a first wiring and a second wiring such that the first wiring and the second wiring are vertically arranged.

Abstract: A deposition apparatus for depositing a material on a wafer, the apparatus including a lower shower head; an upper shower head disposed on the lower shower head, the upper shower head facing the lower shower head; and a support structure between the upper shower head and the lower shower head, the wafer being supportable by the support structure, wherein the upper shower head includes upper holes for providing an upper gas onto the wafer, the lower shower head includes lower holes for providing a lower gas onto the wafer, the support structure includes a ring body surrounding the wafer; a plurality of ring support shafts between the ring body and the lower shower head; and a plurality of wafer supports extending inwardly from a lower region of the ring body to support the wafer, and the plurality of wafer supports are spaced apart from one another.

Abstract: A method of manufacturing a semiconductor device includes alternately stacking sacrificial layers and interlayer insulating layers on a substrate, to form a stack structure; forming channels penetrating through the stack structure; forming separation regions penetrating through the stack structure; forming lateral openings by removing the sacrificial layers through the separation regions; and forming gate electrodes in the lateral openings. Forming the gate electrodes may include forming a nucleation layer in the lateral openings by supplying a source gas and a first reaction gas, and forming a bulk layer on the nucleation layer to fill the lateral openings by supplying the source gas and a second reaction gas, different from the first reaction gas. The first reaction gas may be supplied from a first reaction gas source, stored in a gas charging unit, and supplied from the gas charging unit.

Abstract: A deposition apparatus includes an upper shower head and a lower shower head within a process chamber, the upper shower head and the lower shower head facing each other, a support structure between the upper shower head and the lower shower head, the support structure being connected to the lower shower head to support a wafer, and a plasma process region between the wafer supported by the support structure and the lower shower head, wherein the lower shower head includes lower holes to jet a lower gas in a direction of the wafer, wherein the upper shower head includes upper holes to jet an upper gas in a direction of the wafer, and wherein the support structure includes through opening portions to discharge a portion of the lower gas jetted through the lower holes to a space between the support structure and the upper shower head.

Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include a plurality of gate electrodes that are stacked on a substrate and are spaced apart from each other in a vertical direction and a channel region extending through the plurality of gate electrodes in the vertical direction. Each of the plurality of gate electrodes may include a first conductive layer defining a recess recessed toward the channel region, and a second conductive layer in the recess defined by the first conductive layer. A first concentration of impurities in the second conductive layer may be higher than a second concentration of the impurities in the first conductive layer, and the impurities may include nitrogen (N).

Abstract: A semiconductor memory device may include a substrate, gate electrode structures stacked on the substrate, insulation patterns between the gate electrode structures, vertical channels penetrating through the gate electrode structures and the insulation patterns, and a data storage pattern. The vertical channels may be electrically connected to the substrate. The data storage pattern may be arranged between the gate electrode structures and the vertical channels. Each of the gate electrode structures may include a barrier film, a metal gate, and a crystal grain boundary plugging layer. The crystal grain boundary plugging layer may be between the barrier film and the metal gate.

Abstract: An electrode member according to an embodiment includes a first resin layer; and an electrode layer on the first resin layer, wherein the first resin layer has a thickness in the range of 1 ?m to 25 ?m.

Abstract: A method of manufacturing a semiconductor device includes forming an insulating pattern layer on a substrate, conformally forming a first conductive layer with a first thickness on the insulating pattern layer, wet etching the first conductive layer to have a second thickness that is less than the first thickness, and forming a second conductive layer on the first conductive layer after wet etching the first conductive layer. The second conductive layer includes a material that is different from a material included in the first conductive layer.

Abstract: A memory device may include a gate structure including a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on a substrate, a plurality of etching stop layers, extending from the insulating layers respectively, being on respective lower portions of the gate electrode layers; and a plurality of contacts connected to the gate electrode layers above upper portions of the etching stop layers, respectively, wherein respective ones of the etching stop layers include an air gap therein.

Abstract: Disclosed is a touch window including a substrate, and a sensing electrode on the substrate. The sensing electrode comprises a plurality of sensing parts having directionalities different from each other.