Abstract: A deposition apparatus includes a chamber, a plate in the chamber and configured support a substrate, a deposition unit configured to perform a deposition process in-situ in the chamber, and a UV annealing unit configured to perform a first ultraviolet (UV) and a second ultraviolet (UV) annealing process in-situ in the chamber. The deposition process may include sequentially depositing a first sacrificial layer, a first oxide layer, a second sacrificial layer and a second oxide layer on the substrate. The first UV annealing process may be performed on the first oxide layer after the first oxide layer is deposited. The second UV annealing process may be different from the first UV annealing process and may be performed on the second oxide layer after the second oxide layer is deposited.

Abstract: A deposition apparatus includes a chamber, a plate in the chamber and configured support a substrate, a deposition unit configured to perform a deposition process in-situ in the chamber, and a UV annealing unit configured to perform a first ultraviolet (UV) and a second ultraviolet (UV) annealing process in-situ in the chamber. The deposition process may include sequentially depositing a first sacrificial layer, a first oxide layer, a second sacrificial layer and a second oxide layer on the substrate. The first UV annealing process may be performed on the first oxide layer after the first oxide layer is deposited. The second UV annealing process may be different from the first UV annealing process and may be performed on the second oxide layer after the second oxide layer is deposited.

Abstract: A memory device may include a gate structure including a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on a substrate, a plurality of etching stop layers, extending from the insulating layers respectively, being on respective lower portions of the gate electrode layers; and a plurality of contacts connected to the gate electrode layers above upper portions of the etching stop layers, respectively, wherein respective ones of the etching stop layers include an air gap therein.

Abstract: A method of manufacturing a semiconductor device includes forming an insulating pattern layer on a substrate, conformally forming a first conductive layer with a first thickness on the insulating pattern layer, wet etching the first conductive layer to have a second thickness that is less than the first thickness, and forming a second conductive layer on the first conductive layer after wet etching the first conductive layer. The second conductive layer includes a material that is different from a material included in the first conductive layer.

Abstract: A touch window according to the present invention comprises: a cover substrate; a resin layer on the cover substrate; a substrate on the resin layer; and an electrode on the substrate, wherein the resin layer is arranged with a thickness of 1 ?m to 10 ?m to prevent external defects that can occur when the touch window is bent or folded, such as exposure of the resin layer, or separation or damage to the cover substrate or substrate, thereby allowing improved reliability to be exhibited.

Abstract: A semiconductor device includes a first interlayer insulating layer and a second interlayer insulating layer, and a horizontal conductive pattern interposed between the first interlayer insulating layer and the second interlayer insulating layer. Vertical structures extend through the first interlayer insulating layer, the second interlayer insulating layer, and the horizontal conductive pattern. Each of the first interlayer insulating layer and the second interlayer insulating layer has regions of different impurity concentrations.

Abstract: A semiconductor device includes a first interlayer insulating layer and a second interlayer insulating layer, and a horizontal conductive pattern interposed between the first interlayer insulating layer and the second interlayer insulating layer. Vertical structures extend through the first interlayer insulating layer, the second interlayer insulating layer, and the horizontal conductive pattern. Each of the first interlayer insulating layer and the second interlayer insulating layer has regions of different impurity concentrations.

Abstract: An electrode member according to an embodiment includes a first resin layer; and an electrode layer on the first resin layer, wherein the first resin layer has a thickness in the range of 1 ?m to 25 ?m.

Abstract: A band type sensor includes a substrate and a gesture sensor on the substrate, where the gesture sensor senses the gesture of a user in a capacitive type. And a wearable device having the band type sensor includes a main body, a display part disposed inside the main body, a band connected to the main body, a band type sensor including a touch sensor disposed on the display part and a gesture sensor disposed in the band, and a control unit to perform an operation according to touch and gesture inputs of the user sensed by the band type sensor.

Abstract: A touch window includes a substrate and an electrode structure on the substrate. The electrode structure includes an electrode layer on the substrate, and a resin layer on the electrode layer. The electrode layer includes a sensing electrode and a wire electrode, and the electrode structure has chromaticness indices (b*) of 0 (zero) or more.

Abstract: A touch panel according to the embodiment includes a substrate including an effective area and a dummy area surrounding the effective area; and an outer dummy layer in the dummy area; a planar layer on the substrate; and a transparent electrode disposed on the substrate to detect a position.

Abstract: Disclosed is a touch window including a substrate, and a sensing electrode on the substrate. The sensing electrode comprises a plurality of sensing parts having directionalities different from each other.

Abstract: A touch window according to one embodiment comprises: a substrate having an effective area and an ineffective area; a sensing electrode arranged in the effective area and sensing a position; and a wiring arranged in the effective area and the ineffective area and electrically connecting to the sensing electrode, wherein the wiring comprises a first wiring and a second wiring such that the first wiring and the second wiring are vertically arranged.

Abstract: A touch panel according to the embodiment includes a substrate including an effective area and a dummy area surrounding the effective area; and an outer dummy layer in the dummy area; a planar layer on the substrate; and a transparent electrode disposed on the substrate to detect a position.

Abstract: An interconnection structure having an oxygen trap pattern in a semiconductor device, and a method of fabricating the same are provided. The interconnection structure includes a lower interlayer insulating layer formed on a semiconductor substrate. A metal layer pattern and a capping layer pattern are sequentially stacked on the lower interlayer insulating layer. An oxygen trap pattern is disposed on the capping layer pattern and includes a conductive oxygen trap pattern.

Abstract: The present invention provides methods of forming a phase-change material layer including providing a substrate and a chalcogenide target including germanium (Ge), antimony (Sb) and tellurium (Te) at a temperature wherein tellurium is volatilized and antimony is not volatilized, and performing a sputtering process to form the phase-change material layer including a chalcogenide material on the substrate. Methods of manufacturing a phase-change memory device using the same are also provided.

Abstract: Methods of fabricating integrated circuit memory cells and integrated circuit memory cells are disclosed. An integrated circuit memory cell can be fabricated by forming an ohmic layer on an upper surface of a conductive structure and extending away from the structure along at least a portion of a sidewall of an opening in an insulation layer. An electrode layer is formed on the ohmic layer. A variable resistivity material is formed on the insulation layer and electrically connected to the electrode layer.

Abstract: The present invention relates to fullerene derivatives and an organic electronic device using the same, and more specifically, to a novel fullerene derivative incorporating an aromatic fused ring compound and to an organic electronic device with excellent electrical properties by employing the fullerene derivative. In more detail, the novel fullerene derivative incorporating an aromatic fused ring compound according to the present invention exhibits excellent solubility in organic solvents and has a high electrochemical electron mobility and a high LUMO energy level, thereby making the fullerene derivative a suitable material for organic solar cells featuring a high open circuit voltage (Voc) and an improved energy conversion efficiency, or applicable for use in organic electronic devices such as organic thin film transistors.

Abstract: A phase-change memory device, including a lower electrode, a phase-change material pattern electrically connected to the lower electrode, and an upper electrode electrically connected to the phase-change material pattern. The lower electrode may include a first structure including a metal semiconductor compound, a second structure on the first structure, the second structure including a metal nitride material, and including a lower part having a greater width than an upper part, and a third structure including a metal nitride material containing an element X, the third structure being on the second structure, the element X including at least one selected from the group of silicon, boron, aluminum, oxygen, and carbon.

Abstract: A phase change memory device includes a current restrictive element interposed between an electrically conductive element and a phase change material. The current restrictive element includes a plurality of overlapping film patterns, each of which having a respective first portion proximal to the conductive element and a second portion proximal to the phase change material. The second portions are configured and dimensioned to have higher resistance than the first portions.