Patents by Inventor Hyun-Sik Park

Hyun-Sik Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080220543
    Abstract: A method for fabricating a semiconductor device includes forming a fuse over a substrate, the fuse having a barrier layer, a metal layer, and an anti-reflective layer stacked, selectively removing the anti-reflective layer, forming an insulation layer over a whole surface of the resultant structure including the fuse, and performing repair-etching such that part of the insulation layer remains above the fuse.
    Type: Application
    Filed: December 20, 2007
    Publication date: September 11, 2008
    Inventors: Hyun-Sik Park, Hae-Jung Lee, Jae-Kyun Lee
  • Publication number: 20080160718
    Abstract: A method for fabricating an isolation layer in a semiconductor device includes providing a substrate, forming a trench over the substrate, forming a liner nitride layer and a liner oxide layer along a surface of the trench, forming an insulation layer having an etch selectivity ratio different from that of the liner oxide layer over the liner oxide layer, forming a spin on dielectric (SOD) oxide layer to fill a portion of the trench over the insulation layer, and forming a high density plasma (HDP) oxide layer for filling the remaining a portion of the trench.
    Type: Application
    Filed: December 18, 2007
    Publication date: July 3, 2008
    Inventors: Hae-Jung Lee, Hyun-Sik Park, Jae-Kyun Lee
  • Publication number: 20080128799
    Abstract: A method for fabricating a semiconductor device includes etching a substrate to form a first recess having a micro trench, etching the substrate disposed under the first recess to form a second recess having a profile substantially vertical and a width greater than a portion of the first recess where no micro trench is formed, etching the substrate disposed under the second recess to form a third recess having a profile substantially spherical, and forming a gate pattern over a resultant recess including the first to third recesses.
    Type: Application
    Filed: June 26, 2007
    Publication date: June 5, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Hyun-Sik PARK, Ky-Hyun HAN
  • Patent number: 6734528
    Abstract: The present invention discloses an improved transistor with a &pgr;-gate structure usable at microwave and millimeter wave and comprises a GaAs wafer, GND formed on the bottom surface of the wafer and grounded to source layers formed on the top surface of the wafer by the process of back-side via-hole. A drain is formed on the top surface of the wafer between the source layers and has an air layer on top. A gate, shaped as a result of using an air bridge technique, contacts the top surface of the wafer between the source layers and the drain so as to support the wafer at laterally opposite ends over the air layer of the drain. The gate having &pgr;-structure improves noise characteristics of the transistor because of low electrical resistance, which is a result of the gate structure straddling above the drain stage.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: May 11, 2004
    Inventors: Jin-Koo Rhee, Hyun-Sik Park, Dan An, Yeon-Sik Chae
  • Publication number: 20040083441
    Abstract: A method of generating a net-list for designing an integrated circuit device is provided, including generating a pin template file by laying out logic elements included in the integrated circuit device, generating a pin file by assigning a serial number to the logic elements and setting power names necessary for operating the logic elements, and generating a power inform template file by grouping an internal circuit of the integrated circuit device by a unit of power, generating a power inform file by combining the pin file with the power inform template file and arranging power information which is separately applied to each logic element, generating a final power inform file by assigning correct power names to power ports, to which power applied thereto is not defined, and completing a final net-list by combining core-related information of the integrated circuit device with the final power inform file.
    Type: Application
    Filed: May 19, 2003
    Publication date: April 29, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Gweon, Jin-Yong Lee, Yong-Kwan Kim, Hyun-Sik Park, Hye-Kyong Song
  • Publication number: 20020063293
    Abstract: The present invention proposes a improved transistor with &pgr;-gate structure usable at microwave and millimeter wave and a method for producing the same.
    Type: Application
    Filed: January 4, 2001
    Publication date: May 30, 2002
    Inventors: Jin-Koo Rhee, Hyun-Sik Park, Dan An, Yeon-Sik Chae
  • Patent number: 5761262
    Abstract: A passive containment cooling system for a nuclear reactor and a method of cooling a pressurized water reactor thereby has an isolation condensing means for cooling and condensing steam and accumulating and cooling noncondensable gas released from within a containment of a nuclear reactor. A steam-driven air ejector which is driven by steam of high temperature and pressure generated from a steam generator is used to exhaust the noncondensable gas from the isolation condensing means, to flow the noncondensable gas into the containment. A steam generator makeup water storage tank makes up the water inventory of the steam generator and provides security for steam generator water inventory lost by operation of the steam-driven air ejector. This leads to the removal of early decay heat by dumping steam from the steam generator into the tank and injection of makeup water into the steam generator during the early stage of an accident.
    Type: Grant
    Filed: December 2, 1996
    Date of Patent: June 2, 1998
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Hee-Cheon No, Soon-Heung Chang, Hyun-Sik Park