Patents by Inventor Hyung-Bok Choi
Hyung-Bok Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7858483Abstract: A method for forming a capacitor of a semiconductor device includes forming a first insulation layer having a storage node plug on a semiconductor substrate; forming an etch stop layer and a second insulation layer sequentially on the substrate having the first insulation layer; forming a hole exposing a portion of the storage node plug by selectively etching the second insulation layer by using the etch stop layer; recessing a portion of the storage node plug exposed by the hole; forming a barrier metal layer on a surface of the recessed storage node plug; forming a storage node electrode connected to the storage node plug through the barrier metal layer in the hole; and forming a dielectric layer and a metal layer for a plate electrode sequentially on the storage node electrode.Type: GrantFiled: June 15, 2005Date of Patent: December 28, 2010Assignee: Hynix Semiconductor Inc.Inventors: Hyung Bok Choi, Jong Bum Park, Kee Jeung Lee, Jong Min Lee
-
Patent number: 7820507Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes: an inter-layer dielectric (ILD) layer formed on a semiconductor substrate; a contact plug formed in the ILD layer, such that a predetermined portion of the contact plug protrudes above the ILD layer; an etch stop layer formed on the ILD layer exposing a top portion of the contact plug; and a bottom electrode of a capacitor formed partially in the etch stop layer to be isolated from the ILD layer by the etch stop layer and the contact plug to prevent a direct contact with the ILD layer, and to be partially contacted with the contact plug.Type: GrantFiled: December 6, 2005Date of Patent: October 26, 2010Assignee: Hynix Semiconductor Inc.Inventor: Hyung-Bok Choi
-
Patent number: 7666738Abstract: The present invention relates to a method for fabricating a capacitor of a semiconductor device. The method includes the steps of: forming a first amorphous silicon layer doped with an impurity in a predetermined first doping concentration suppressing dopants from locally agglomerating; forming an impurity undoped second amorphous silicon layer on the first amorphous silicon layer in an in-situ condition; forming a storage node by patterning the first amorphous silicon layer and the second amorphous silicon layer; forming silicon grains on a surface of the storage node; and doping the impurity to the storage node and the silicon grains until reaching a second predetermined concentration for providing conductivity required by the storage node.Type: GrantFiled: December 7, 2007Date of Patent: February 23, 2010Assignee: Hynix Semiconductor Inc.Inventors: Dong-Woo Shin, Hyung-Bok Choi, Jong-Min Lee, Jin-Woong Kim
-
Patent number: 7595526Abstract: A method for manufacturing a capacitor in a semiconductor device for securing capacitance without a merging phenomenon during a MPS grain growth process. The manufacturing step begins with a preparation of a substrate. The interlayer dielectric (ILD) layer is formed on the substrate and is etched to form conductive plug. Then, an etch barrier layer and a sacrifice insulating layer are formed on entire surface subsequently. A cylinder typed first electrode is formed over the conductive plug using the sacrifice insulating layer. Thereafter, first meta-stable poly silicon (MPS) grains are formed on inner wall of the first electrode except a bottom region thereof. However, second MPS grains with small sizes can be formed in the bottom region for increasing a storage area of the first electrode. Finally, a dielectric layer and a second electrode are formed on the first electrode subsequently.Type: GrantFiled: August 11, 2005Date of Patent: September 29, 2009Assignee: Hynix Semiconductor Inc.Inventors: Dong-Woo Shin, Hyung-Bok Choi
-
Patent number: 7547598Abstract: A method for fabricating a capacitor in a semiconductor device includes forming a first insulation layer over a substrate, forming storage node contact plugs in the first insulation layer, contacting predetermined portions of the substrate, forming a second insulation layer over the first insulation layer and the storage node contact plugs, forming trenches exposing the storage node contact plugs, forming storage nodes in the trenches, forming a plasma barrier layer over the second insulation layer and the storage nodes, forming a capping layer over the plasma barrier layer and filled in the trenches, removing the capping layer, the plasma barrier layer, and the second insulation layer, forming a dielectric layer over the storage nodes, and forming a plate electrode over the dielectric layer.Type: GrantFiled: September 12, 2006Date of Patent: June 16, 2009Assignee: Hynix Semiconductor Inc.Inventor: Hyung-Bok Choi
-
Patent number: 7407854Abstract: The present invention relates to a method for fabricating a capacitor of a semiconductor device. The method includes the steps of: forming a first amorphous silicon layer doped with an impurity in a predetermined first doping concentration suppressing dopants from locally agglomerating; forming an impurity undoped second amorphous silicon layer on the first amorphous silicon layer in an in-situ condition; forming a storage node by patterning the first amorphous silicon layer and the second amorphous silicon layer; forming silicon grains on a surface of the storage node; and doping the impurity to the storage node and the silicon grains until reaching a second predetermined concentration for providing conductivity required by the storage node.Type: GrantFiled: December 30, 2003Date of Patent: August 5, 2008Assignee: Hynix Semiconductor Inc.Inventors: Dong-Woo Shin, Hyung-Bok Choi, Jong-Min Lee, Jin-Woong Kim
-
Publication number: 20080076231Abstract: The present invention relates to a method for fabricating a capacitor of a semiconductor device. The method includes the steps of: forming a first amorphous silicon layer doped with an impurity in a predetermined first doping concentration suppressing dopants from locally agglomerating; forming an impurity undoped second amorphous silicon layer on the first amorphous silicon layer in an in-situ condition; forming a storage node by patterning the first amorphous silicon layer and the second amorphous silicon layer; forming silicon grains on a surface of the storage node; and doping the impurity to the storage node and the silicon grains until reaching a second predetermined concentration for providing conductivity required by the storage node.Type: ApplicationFiled: December 7, 2007Publication date: March 27, 2008Applicant: Hynix Semiconductor Inc.Inventors: Dong-Woo SHIN, Hyung-Bok Choi, Jong-Min Lee, Jin-Woong Kim
-
Patent number: 7339211Abstract: Semiconductor devices and methods of manufacture thereof are disclosed that are capable of preventing a short of lower electrodes caused by a leaning or lifting phenomenon while forming the lower electrodes and securing enough capacitance of a capacitor by widening an effective capacitor area. The inventive semiconductor device includes: a plurality of capacitor plugs disposed in an orderly separation distance; and a plurality of lower electrodes used for a capacitor and disposed in an orderly separation distance to be respectively connected with the capacitor plugs.Type: GrantFiled: July 23, 2003Date of Patent: March 4, 2008Assignee: Hynix Semiconductor Inc.Inventors: Dong-Sauk Kim, Ho-Seok Lee, Byung-Jun Park, Il-Young Kwon, Jong-Min Lee, Hyeong-Soo Kim, Jin-Woong Kim, Hyung-Bok Choi, Dong-Woo Shin
-
Patent number: 7285485Abstract: A method for forming a gate in a semiconductor device includes the steps of: providing a substrate having active and field regions; selectively etching a portion of the active region to form a trench; forming on the substrate including the trench an amorphous conductive film for forming a gate; subjecting the resulting structure to an annealing process so as to convert the amorphous conductive film into a crystalline conductive film; and selectively etching the crystalline conductive film so as to form a gate covering the corner portion of the trench.Type: GrantFiled: June 17, 2005Date of Patent: October 23, 2007Assignee: Hynix Semiconductor Inc.Inventors: Yun Seok Chun, Hyung Bok Choi
-
Patent number: 7259057Abstract: Disclosed is a method for forming a capacitor of a semiconductor device capable of improving the film quality of a dielectric film. The method includes the steps of providing a semiconductor substrate having a storage node contact; forming a metal storage electrode on the substrate; forming a dielectric film using any one chosen from a group including a single film made of HfO2, a single film made of Al2O3, and a lamination film made of HfO2 and Al2O3 on the metal storage electrode; performing CF4 plasma treatment on the dielectric film; and forming a metal plate electrode on the dielectric film.Type: GrantFiled: May 6, 2005Date of Patent: August 21, 2007Assignee: Hynix Semiconductor Inc.Inventor: Hyung Bok Choi
-
Publication number: 20070161200Abstract: A method for fabricating a capacitor in a semiconductor device includes forming a first insulation layer over a substrate, forming storage node contact plugs in the first insulation layer, contacting predetermined portions of the substrate, forming a second insulation layer over the first insulation layer and the storage node contact plugs, forming trenches exposing the storage node contact plugs, forming storage nodes in the trenches, forming a plasma barrier layer over the second insulation layer and the storage nodes, forming a capping layer over the plasma barrier layer and filled in the trenches, removing the capping layer, the plasma barrier layer, and the second insulation layer, forming a dielectric layer over the storage nodes, and forming a plate electrode over the dielectric layer.Type: ApplicationFiled: September 12, 2006Publication date: July 12, 2007Inventor: Hyung-Bok Choi
-
Publication number: 20070085128Abstract: Semiconductor devices and methods of manufacture thereof are disclosed that are capable of preventing a short of lower electrodes caused by a leaning or lifting phenomenon while forming the lower electrodes and securing enough capacitance of a capacitor by widening an effective capacitor area. The inventive semiconductor device includes: a plurality of capacitor plugs disposed in an orderly separation distance; and a plurality of lower electrodes used for a capacitor and disposed in an orderly separation distance to be respectively connected with the capacitor plugs.Type: ApplicationFiled: December 8, 2006Publication date: April 19, 2007Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Dong-Sauk KIM, Ho-Seok Lee, Byung-Jun Park, Il-Young Kwon, Jong-Min Lee, Hyeong-Soo Kim, Jin-Woong Kim, Hyung-Bok Choi, Dong-Woo Shin
-
Publication number: 20070045703Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes: an inter-layer dielectric (ILD) layer formed on a semiconductor substrate; a contact plug formed in the ILD layer, such that a predetermined portion of the contact plug protrudes above the ILD layer; an etch stop layer formed on the ILD layer exposing a top portion of the contact plug; and a bottom electrode of a capacitor formed partially in the etch stop layer to be isolated from the ILD layer by the etch stop layer and the contact plug to prevent a direct contact with the ILD layer, and to be partially contacted with the contact plug.Type: ApplicationFiled: December 6, 2005Publication date: March 1, 2007Inventor: Hyung-Bok Choi
-
Patent number: 7115468Abstract: A semiconductor device and a fabricating method for the same are disclosed, in which when forming a capacitor sacrificial film pattern, even if a misalignment occurs, the degradation of the dielectric property due to a direct contact between the contact plug and the dielectric medium can be prevented. The semiconductor device includes a connecting part connected through an insulating layer of a substrate to a conductive layer, a seed separating layer formed around the connecting part and the insulating layer to provide an open region exposing at least part of the connecting part, a seed layer filled into the open region of the seed separating layer and a capacitor. The capacitor includes of a lower electrode formed upon the seed layer, a dielectric medium formed upon the lower electrode, and an upper electrode formed upon the dielectric medium.Type: GrantFiled: May 31, 2005Date of Patent: October 3, 2006Assignee: Hynix Semiconductor Inc.Inventor: Hyung-Bok Choi
-
Publication number: 20050269618Abstract: A method for manufacturing a capacitor in a semiconductor device for securing capacitance without a merging phenomenon during a MPS grain growth process. The manufacturing step begins with a preparation of a substrate. The interlayer dielectric (ILD) layer is formed on the substrate and is etched to form conductive plug. Then, an etch barrier layer and a sacrifice insulating layer are formed on entire surface subsequently. A cylinder typed first electrode is formed over the conductive plug using the sacrifice insulating layer. Thereafter, first meta-stable poly silicon (MPS) grains are formed on inner wall of the first electrode except a bottom region thereof. However, second MPS grains with small sizes can be formed in the bottom region for increasing a storage area of the first electrode. Finally, a dielectric layer and a second electrode are formed on the first electrode subsequently.Type: ApplicationFiled: August 11, 2005Publication date: December 8, 2005Inventors: Dong-Woo Shin, Hyung-Bok Choi
-
Publication number: 20050233520Abstract: A semiconductor device and a fabricating method for the same are disclosed, in which when forming a capacitor sacrificial film pattern, even if a misalignment occurs, the degradation of the dielectric property due to a direct contact between the contact plug and the dielectric medium can be prevented. The semiconductor device includes a connecting part connected through an insulating layer of a substrate to a conductive layer, a seed separating layer formed around the connecting part and the insulating layer to provide an open region exposing at least part of the connecting part, a seed layer filled into the open region of the seed separating layer and a capacitor. The capacitor includes of a lower electrode formed upon the seed layer, a dielectric medium formed upon the lower electrode, and an upper electrode formed upon the dielectric medium.Type: ApplicationFiled: May 31, 2005Publication date: October 20, 2005Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Hyung-Bok Choi
-
Patent number: 6946356Abstract: A method for manufacturing a capacitor in a semiconductor device for securing capacitance without a merging phenomenon during a MPS grain growth process. The manufacturing step begins with a preparation of a substrate. The interlayer dielectric (ILD) layer is formed on the substrate and is etched to form conductive plug. Then, an etch barrier layer and a sacrifice insulating layer are formed on entire surface subsequently. A cylinder typed first electrode is formed over the conductive plug using the sacrifice insulating layer. Thereafter, first meta-stable poly silicon (MPS) grains are formed on inner wall of the first electrode except a bottom region thereof. However, second MPS grains with small sizes can be formed in the bottom region for increasing a storage area of the first electrode. Finally, a dielectric layer and a second electrode are formed on the first electrode subsequently.Type: GrantFiled: December 12, 2002Date of Patent: September 20, 2005Assignee: Hynix Semiconductor Inc.Inventors: Dong-Woo Shin, Hyung-Bok Choi
-
Patent number: 6917114Abstract: A semiconductor device and a fabricating method for the same are disclosed, in which when forming a capacitor sacrificial film pattern, even if a misalignment occurs, the degradation of the dielectric property due to a direct contact between the contact plug and the dielectric medium can be prevented. The semiconductor device includes a connecting part connected through an insulating layer of a substrate to a conductive layer, a seed separating layer formed around the connecting part and the insulating layer to provide an open region exposing at least part of the connecting part, a seed layer filled into the open region of the seed separating layer and a capacitor. The capacitor includes of a lower electrode formed upon the seed layer, a dielectric medium formed upon the lower electrode, and an upper electrode formed upon the dielectric medium.Type: GrantFiled: January 22, 2002Date of Patent: July 12, 2005Assignee: Hynix Semiconductor Inc.Inventor: Hyung-Bok Choi
-
Publication number: 20050018525Abstract: Semiconductor devices and methods of manufacture thereof are disclosed that are capable of preventing a short of lower electrodes caused by a leaning or lifting phenomenon while forming the lower electrodes and securing enough capacitance of a capacitor by widening an effective capacitor area. The inventive semiconductor device includes: a plurality of capacitor plugs disposed in an orderly separation distance; and a plurality of lower electrodes used for a capacitor and disposed in an orderly separation distance to be respectively connected with the capacitor plugs.Type: ApplicationFiled: July 23, 2003Publication date: January 27, 2005Inventors: Dong-Sauk Kim, Ho-Seok Lee, Byung-Jun Park, Il-Young Kwon, Jong-Min Lee, Hyeong-Soo Kim, Jin-Woong Kim, Hyung-Bok Choi, Dong-Woo Shin
-
Patent number: 6818497Abstract: The present invention relates to a method for fabricating a capacitor of a semiconductor memory device using an electrochemical deposition. The method in accordance with the present invention includes the steps of forming a contact hole in an insulating layer formed on a substrate; forming a plug in the contact hole, wherein the plug contains a nitride layer; forming a seed layer on the insulating layer and in the contact hole; forming a sacrificial layer including a trench overlapped with the contact hole; forming a Ru bottom electrode in the trench with electrochemical deposition; removing the sacrificial layer and exposing the Ru bottom electrode, wherein the seed layer not covered with the Ru bottom electrode is exposed; removing the exposed seed layer; forming a dielectric layer on the Ru bottom electrode; and forming a top electrode on the dielectric layer.Type: GrantFiled: December 30, 2002Date of Patent: November 16, 2004Assignee: Hynix Semiconductor INCInventors: Chang-Rock Song, Hyung-Bok Choi