Abstract: A memory device includes: first conductive lines extending in a first direction; second conductive lines extending in a second direction intersecting the first direction; a plurality of memory cells disposed at intersection portions of the first conductive lines and the second conductive lines; first selection transistors respectively connected to the first conductive lines, the first selection transistors constituting a plurality of groups; and first discharge circuits respectively connected to the plurality of groups of first selection transistors, each of the first discharge circuits discharging a group of first conductive lines corresponding thereto among the first conductive lines in response to a gate control signal.

Abstract: A memory device includes first to nth decks respectively coupled to first to nth row lines which are stacked over a substrate in a vertical direction perpendicular to a surface of the substrate, n being a positive integer, a first connection structure extending from the substrate in the vertical direction to be coupled to the first row line, even-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of even-numbered row lines among the second to nth row lines, and odd-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of odd-numbered row lines among the second to nth row lines. The even-numbered connection structures are spaced apart from the odd-numbered connection structures with the first row line and the first connection structure that are interposed between the even-numbered connection structures and the odd-numbered connection structures.

Abstract: An electronic device includes a semiconductor memory including material layers each including one or more low-resistance areas and one or more high-resistance areas, insulating layers stacked alternately with the material layers and including protrusions extending more than the material layers, conductive pillars passing through the insulating layers and the low-resistance areas, conductive layers located between the protrusions, and variable resistance layers interposed between the low-resistance areas and the conductive layers.

Abstract: A neuromorphic device is provided. The neuromorphic device may include a pre-synaptic neuron, a synapse electrically connected with the pre-synaptic neuron through a row line, and a post-synaptic neuron electrically connected with the synapse through a column line. The post-synaptic neuron may include a post-neuron circuit and a post-neuron transfer function circuit electrically connected to the column line. The post-neuron transfer function circuit may include a first inverting circuit including at least one first pull-up transistor and at least two first pull-down transistors, the pull-down transistors being electrically connected with each other in parallel.

Abstract: Provided are a compound represented by Formula 1, an organic electric element comprising a first electrode, a second electrode, and an organic material layer formed between the first electrode and the second electrode, and an electronic device thereof, wherein by comprising compound represented by Formula 1 in the organic material layer, the driving voltage of the organic electric element can be lowered, and the luminous efficiency and life time, in particular, life time can be improved.

Abstract: A semiconductor memory includes bit lines, word lines, memory cells coupled between the bit lines and the word lines, and a sensing circuit configured to sense a state of a selected memory cell. During a read operation of the selected memory cell, the electronic device is configured to precharge a selected word line to a first voltage, to precharge an unselected word line to a second voltage, to float the selected word line and the unselected word line, to apply a bit line voltage a selected bit line, to adjust a voltage level of the unselected word line using a first leakage current that flows between an unselected bit line and the unselected word line, to couple the selected word line and the unselected word line to the sensing circuit, and to compare a voltage level of the selected word line with the voltage level of the unselected word line.

Abstract: A semiconductor memory includes bit lines, word lines, memory cells coupled between the bit lines and the word lines, and a sensing circuit configured to sense a state of a selected memory cell. During a read operation of the selected memory cell, the electronic device is configured to precharge a selected word line to a first voltage, to precharge an unselected word line to a second voltage, to float the selected word line and the unselected word line, to apply a bit line voltage a selected bit line, to adjust a voltage level of the unselected word line using a first leakage current that flows between an unselected bit line and the unselected word line, to couple the selected word line and the unselected word line to the sensing circuit, and to compare a voltage level of the selected word line with the voltage level of the unselected word line.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a bit line, a word line crossing the bit line, and a memory cell coupled to and disposed between the bit line and the word line. In a read operation, when the word line, which is in a precharged state, is floated, the bit line is driven to increase a voltage level of the bit line, and stopped when the memory cell is turned on.

Abstract: The present invention provides the compound represented by Formula 1 or Formula A, an organic electric element comprising a first electrode, a second electrode, and an organic material layer formed between the first electrode and the second electrode, and electronic device thereof, and by comprising the compound represented by Formula 1 or Formula A in the organic material layer, the driving voltage of the organic electronic device can be lowered, and the luminous efficiency and life time of the organic electronic device can be improved.

Abstract: A neuromorphic device including a convolution neural network is described. The convolution neural network may include an input layer having a plurality of input pixels, a plurality of kernel resistors, each of the kernel resistors corresponding to one of the plurality of input pixels, and an intermediate layer having a plurality of intermediate pixels electrically connected to the plurality of kernel resistors.

Abstract: A neuromorphic device includes a substrate; a first electrode and a second electrode that are disposed over the substrate, extend in a first direction, and are spaced apart in a second direction; a stack structure between the first electrode and the second electrode, which includes reactive metal layers alternately stacked with one or more insulating layers; an oxygen-containing layer between the first electrode and the stack structure, which includes oxygen ions; and an oxygen diffusion-retarding layer between the stack structure and the oxygen-containing layer. The first direction is perpendicular to a top surface of the substrate, and the second direction is parallel to the top surface of the substrate. Each reactive metal layer may react with the oxygen ions to form a dielectric oxide layer. The oxygen diffusion-retarding layer interferes with a movement of the oxygen ions. A thickness of the oxygen diffusion-retarding layer varies along the first direction.

Abstract: A neuromorphic device includes a synapse. The synapse includes a first electrode, a second electrode spaced apart from the first electrode, an oxygen-containing layer disposed between the first electrode and the second electrode, the oxygen-containing layer including oxygen ions, and a stack structure disposed between the oxygen-containing layer and the second electrode, the stack structure including a plurality of reactive metal layers alternately arranged with a plurality of oxygen diffusion-retarding layers. The plurality of reactive metal layers are capable of reacting with oxygen ions of the oxygen-containing layer. The plurality of oxygen diffusion-retarding layers interfere with a movement of the oxygen ions from the oxygen-containing layer to the plurality of reactive metal layers.

Abstract: A method for updating a weight of a synapse of a neuromorphic device is provided. The synapse may include a transistor and a memristor. The memristor may have a first electrode coupled to a source electrode of the transistor. The method may include inputting a row spike to a drain electrode of the transistor at a first time; inputting a column spike to a second electrode of the memristor at a second time; inputting a row pulse to the drain electrode of the transistor at a third time that is delayed by a first delay time from the second time; inputting a column pulse to the second electrode of the memristor at a fourth time that is delayed by a second delay time from the second time; and inputting a gating pulse to a gate electrode of the transistor at a fifth time that is delayed by a third delay time from the fourth time.

Abstract: A neuromorphic device includes a synapse. The synapse, according to an embodiment, includes a first electrode, a second electrode spaced apart from the first electrode, an oxygen-containing layer disposed between the first electrode and the second electrode, the oxygen-containing layer including oxygen ions, and a reactive metal layer disposed between the oxygen-containing layer and the second electrode. The oxygen-containing layer includes oxygen ions. The reactive metal layer is capable of reacting with the oxygen ions of the oxygen-containing layer. A width of the reactive metal layer decreases along a direction toward the oxygen-containing layer from the second electrode.

Abstract: A neuromorphic device includes a synapse. The synapse includes a first electrode, a second electrode spaced apart from the first electrode, an oxygen-containing layer disposed between the first electrode and the second electrode, a reactive metal layer disposed between the oxygen-containing layer and the second electrode, and an oxygen diffusion-retarding layer disposed between the reactive metal layer and the oxygen-containing layer. The oxygen-containing layer includes a P-type material and oxygen ions. The reactive metal layer reacts with the oxygen ions of the oxygen-containing layer. The oxygen diffusion-retarding layer includes an N-type material and interferes with a movement of the oxygen ions from the oxygen-containing layer to the reactive metal layer. An interface between the oxygen-containing layer and the oxygen diffusion-retarding layer is a P-N junction.

Abstract: A neuromorphic device is provided. The neuromorphic device may include a pre-synaptic neuron; a row line extending in a row direction from the pre-synaptic neuron; a post-synaptic neuron; a column line extending in a column direction from the post-synaptic neuron; and a synapse disposed at an intersection between the row line and the column line. The synapse may include a first synapse layer including a plurality of first carbon nano-tubes; a second synapse layer including a plurality of second carbon nano-tubes having different structures from the plurality of first carbon nano-tubes; and a third synapse layer including a plurality of third carbon nano-tubes having different structures from the plurality of first carbon nano-tubes and the plurality of second carbon nano-tubes.

Abstract: A neuromorphic device may include: a plurality of pre-synaptic neurons; row lines extending in a row direction from the plurality of pre-synaptic neurons; a plurality of post-synaptic neurons; column lines extended in a column direction from the plurality of post-synaptic neurons; a plurality of synapses arranged at intersections between the row lines and the column lines; a plurality of first control blocks; and first control lines extending from the control blocks. The first control lines may be electrically connected to the plurality of synapses.

Abstract: A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.

Abstract: A neuromorphic device may include: a pre-synaptic neuron; a plurality of post-synaptic neurons; and a plurality of synapses electrically connected to the pre-synaptic neuron and electrically connected to the plurality of post-synaptic neurons. Each of the post-synaptic neurons may include: an integrator; a main comparator having a first input port connected to an output port of the integrator; and a first sub comparator having a first input port connected to the output port of the integrator.

Abstract: A stacked semiconductor package includes a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pads are arranged, a first encapsulation member, two second semiconductor chips having second active surfaces over which second bonding pads are arranged at one side peripheries and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads, first coupling members interposed between the peripheral bonding pads and the second bonding pads, a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips, and a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and coupled with the central bonding pads.