Patents by Inventor Hyung-Gu Roh

Hyung-Gu Roh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Array substrate including thin film transistor and method of fabricating the same
    Patent number: 8021937
    Abstract: A method of fabricating an array substrate includes: forming a gate line and a gate electrode connected to the gate line; forming a gate insulating layer on the gate line and the gate insulting layer; sequentially forming an intrinsic amorphous silicon pattern and an impurity-doped amorphous silicon pattern on the gate insulating layer over the gate electrode; forming a data line on the gate insulating layer and source and drain electrodes on the impurity-doped amorphous silicon pattern, the data line crossing the gate line to define a pixel region, and the source and drain electrodes spaced apart from each other; removing a portion of the impurity-doped amorphous silicon pattern exposed through the source and drain electrodes to define an ohmic contact layer; irradiating a first laser beam onto the intrinsic amorphous silicon pattern through the source and drain electrode to form an active layer including a first portion of polycrystalline silicon and a second portion of amorphous silicon at both sides of th
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: September 20, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Hyung-Gu Roh, Byung-Chul Ahn, Hee-Dong Choi, Seong-Moh Seo, Jun-Min Lee
  • ARRAY SUBSTRATE INCLUDING THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME
    Publication number: 20100117090
    Abstract: A method of fabricating an array substrate includes: forming a gate line and a gate electrode connected to the gate line; forming a gate insulating layer on the gate line and the gate insulting layer; sequentially forming an intrinsic amorphous silicon pattern and an impurity-doped amorphous silicon pattern on the gate insulating layer over the gate electrode; forming a data line on the gate insulating layer and source and drain electrodes on the impurity-doped amorphous silicon pattern, the data line crossing the gate line to define a pixel region, and the source and drain electrodes spaced apart from each other; removing a portion of the impurity-doped amorphous silicon pattern exposed through the source and drain electrodes to define an ohmic contact layer; irradiating a first laser beam onto the intrinsic amorphous silicon pattern through the source and drain electrode to form an active layer including a first portion of polycrystalline silicon and a second portion of amorphous silicon at both sides of th
    Type: Application
    Filed: June 17, 2009
    Publication date: May 13, 2010
    Inventors: Hyung-Gu Roh, Byung-Chul Ahn, Hee-Dong Choi, Seong-Moh Seo, Jun-Min Lee