Patents by Inventor Hyung Seok Kang
Hyung Seok Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250079197Abstract: Disclosed are an apparatus for treating a substrate and a method of treating a substrate using a supercritical fluid. The apparatus includes: a chamber for providing a treatment space for treating a substrate; and a treatment fluid supply unit for supplying a treatment fluid to the treatment space, in which treatment fluid supply unit includes: a tank for storing the treatment fluid; a heating unit for heating the treatment fluid in the tank to convert the treatment fluid from a first state to a second state; an inlet line for introducing the treatment fluid in the first state into the tank; a supply line for supplying the treatment fluid of the second state from the tank to the chamber; a circulation line for circulating the treatment fluid in the tank; a first valve installed in the circulation line; and a temperature drop member installed in the circulation line to lower a temperature of the treatment fluid flowing through the circulation line.Type: ApplicationFiled: August 27, 2024Publication date: March 6, 2025Applicant: SEMES CO., LTD.Inventors: Pil Kyun HEO, Min Woo KIM, Hyung Seok KANG, Anton KORIAKIN, Joon Hee LEE
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Publication number: 20230173526Abstract: Proposed are a home port, and a substrate processing apparatus and a home port cleaning method using the same. The home port includes a housing supported by a holder and having a space therein, a nozzle holder provided at an upper portion of the housing and mounting a nozzle for discharging a process liquid to a substrate, an inclined surface formed below the nozzle holder in the space, an exhaust hole exhausting fumes generated in the space of the housing, a rinse supply hole supplying a rinse liquid for removing a residual process liquid remaining on the inclined surface, a hinge provided at a lower portion of the housing and hingedly coupling the housing and the holder to enable rotation of the housing, and an actuating means rotating the housing in a direction in which the inclined surface is parallel to a ground surface on which the housing is installed.Type: ApplicationFiled: December 1, 2022Publication date: June 8, 2023Applicant: SEMES CO., LTD.Inventors: Young Jun SON, Hyung Seok KANG, Min Woo KIM
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Publication number: 20230113184Abstract: The present disclosure relates to a flow resistance generating unit that generates a flow resistance in a pipe to solve a flow imbalance problem due to a bent pipe and stabilizes an internal airflow, and a substrate treating apparatus including the same. The substrate treating apparatus comprises a fluid supply unit for supplying fluid for treating a substrate and including an upper fluid supply module for supplying the fluid to an upper portion of the substrate, a lower fluid supply module for supplying the fluid to a lower portion of the substrate, and a supply pipe connected to at least one of the upper fluid supply module and the lower fluid supply module, and a flow resistance generating unit installed in the supply pipe and for generating a flow resistance with respect to the fluid passing through the supply pipe.Type: ApplicationFiled: July 15, 2022Publication date: April 13, 2023Inventors: Jae Won SHIN, Jae Seong LEE, Hae Won CHOI, Joon Ho WON, Koriakin ANTON, Min Woo KIM, Hyung Seok KANG, Eung Su KIM, Pil Kyun HEO, Jin Yeong SUNG
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Patent number: 7843736Abstract: Disclosed is a read method of a non-volatile memory device which includes performing a first read operation in which a first read voltage is applied to a selected word line. If a read fail arises at the first read operation, a second read operation is performed in which a second read voltage lower than the first read voltage is applied to the selected word line. If no read fail arises at the second read operation, the read fail generated at the first read operation is cured by performing a program operation.Type: GrantFiled: March 3, 2009Date of Patent: November 30, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-Seok Kang, Eui-Gyu Han, Hoo-Sung Kim
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Patent number: 7813184Abstract: Methods of performing multi-block erasing operations on a memory device that includes a plurality of memory blocks are provided. Pursuant to these methods, the rate at which a first voltage that is applied to the memory blocks that are to be erased during the multi-block erasing operation rises is controlled based on the number of memory blocks that are to be erased. The memory device may be a flash memory device, and the first voltage may be an erasing voltage that is applied to a substrate of the flash memory device. The rate at which the first voltage rises may be set so that the substrate of the flash memory device reaches the erasing voltage level at approximately the same time regardless of the number of memory blocks that are to be erased.Type: GrantFiled: December 21, 2006Date of Patent: October 12, 2010Assignee: Samsung Electronics Co. Ltd.Inventors: Hoo-Sung Kim, Hyung-Seok Kang, Jin-Yub Lee
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Publication number: 20090231922Abstract: Disclosed is a read method of a non-volatile memory device which includes performing a first read operation in which a first read voltage is applied to a selected word line. If a read fail arises at the first read operation, a second read operation is performed in which a second read voltage lower than the first read voltage is applied to the selected word line. If no read fail arises at the second read operation, the read fail generated at the first read operation is cured by performing a program operation.Type: ApplicationFiled: March 3, 2009Publication date: September 17, 2009Inventors: Hyung-Seok Kang, Eui-Gyu Han, Hoo-Sung Kim
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Publication number: 20090052252Abstract: Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage.Type: ApplicationFiled: October 20, 2008Publication date: February 26, 2009Inventors: Hyung-seok Kang, Eui-gyu Han, Gyeong-soo Han, Jin-yub Lee, Hoo-sung Kim
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Patent number: 7457160Abstract: Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage.Type: GrantFiled: December 8, 2006Date of Patent: November 25, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung-seok Kang, Eui-gyu Han, Gyeong-soo Han, Jin-yub Lee, Hoo-sung Kim
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Publication number: 20080101122Abstract: Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage.Type: ApplicationFiled: December 8, 2006Publication date: May 1, 2008Inventors: Hyung-seok Kang, Eui-gyu Han, Gyeong-soo Han, Jin-yub Lee, Hoo-sung Kim
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Publication number: 20080074931Abstract: Methods of performing multi-block erasing operations on a memory device that includes a plurality of memory blocks are provided. Pursuant to these methods, the rate at which a first voltage that is applied to the memory blocks that are to be erased during the multi-block erasing operation rises is controlled based on the number of memory blocks that are to be erased. The memory device may be a flash memory device, and the first voltage may be an erasing voltage that is applied to a substrate of the flash memory device. The rate at which the first voltage rises may be set so that the substrate of the flash memory device reaches the erasing voltage level at approximately the same time regardless of the number of memory blocks that are to be erased.Type: ApplicationFiled: December 21, 2006Publication date: March 27, 2008Inventors: Hoo-Sung Kim, Hyung-Seok Kang, Jin-Yub Lee
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Publication number: 20040180082Abstract: Disclosed herein is submicron-liposome containing highly concentrated triterpenoid prepared by using non-toxic solvent without intense mechanical treatment and a method for preparing the same.Type: ApplicationFiled: October 2, 2003Publication date: September 16, 2004Applicant: AMOREPACIFIC CORPORATIONInventors: Hyung-seok Kang, Gae-Won Nam, Sang-Hoon Han, Ih-Seop Chang
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Patent number: 6569528Abstract: There are provided amphiphilic biodegradable block copolymers comprising polyethylenimine (PEI) as a hydrophilic block and aliphatic polyesters as a hydrophobic block, which can form various size of polymer aggregates and have very low critical micelle concentration, approximately 10−3 g/l in comparison with low-molecular-weight micelle, and self-assembled polymer aggregates formed from the block copolymers in aqueous milieu, which can be applied to solubilization of insoluble drug and a delivery system of proteins, genes or drugs.Type: GrantFiled: June 19, 2002Date of Patent: May 27, 2003Assignee: Pacific CorporationInventors: Yoon Sung Nam, Hyung Seok Kang, Sang Hoon Han, Ih Seop Chang
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Publication number: 20030009004Abstract: There are provided amphiphilic biodegradable block copolymers comprising polyethylenimine (PEI) as a hydrophilic block and aliphatic polyesters as a hydrophobic block, which can form various size of polymer aggregates and have very low critical micelle concentration, approximately 10−3 g/l in comparison with low-molecular-weight micelle, and self-assembled polymer aggregates formed from the block copolymers in aqueous milieu, which can be applied to solubilization of insoluble drug and a delivery system of proteins, genes or drugs.Type: ApplicationFiled: June 19, 2002Publication date: January 9, 2003Inventors: Yoon Sung Nam, Hyung Seok Kang, Sang Hoon Han, Ih Seop Chang