Patents by Inventor I-Hsieh Wong

I-Hsieh Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10957784
    Abstract: A method of manufacturing a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers on a substrate. The first and second semiconductor layers include first end portions on either side of a second portion along a length of the first and second semiconductor layers. The first and second semiconductor layers are formed of different materials. The second portion of the first semiconductor layers is removed to form spaces. A mask layer is formed over the second portion of an uppermost second semiconductor layer above the spaces. The first portions of first and second semiconductor layers are irradiated with radiation from a radiation source to cause material from the first portions of the first and second semiconductor layers to combine with each other.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: March 23, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: I-Hsieh Wong, Samuel C. Pan, Chee-Wee Liu, Huang-Siang Lan, Chung-En Tsai, Fang-Liang Lu
  • Publication number: 20210066500
    Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.
    Type: Application
    Filed: May 21, 2020
    Publication date: March 4, 2021
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Kai-Hsuan Lee, I-Hsieh Wong, Cheng-Yu Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Syun-Ming Jang, Meng-Han Chou
  • Publication number: 20210036122
    Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a first metal gate stack disposed over the stack of semiconductor layers, a second metal gate stack interleaved between the stack of semiconductor layers, a source/drain (S/D) feature disposed in the stack of semiconductor layers, and an S/D contact disposed over the S/D feature. In many examples, the S/D feature is separated from a sidewall of the second metal gate stack by a first air gap and the S/D contact is separated from a sidewall of the first metal gate stack by a second air gap.
    Type: Application
    Filed: April 16, 2020
    Publication date: February 4, 2021
    Inventors: I-Hsieh Wong, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20200411667
    Abstract: A semiconductor structure and a method of fabricating thereof is provided. The semiconductor structure may include a plurality of channel layers disposed over a semiconductor substrate, a plurality of metal gate (MGs) each disposed between two channel layers, an inner spacer disposed on a sidewall of each MG, a source/drain (S/D) feature disposed adjacent to the plurality of MGs, and a low-k dielectric feature disposed on the inner spacer, where the low-k dielectric feature extends into the S/D feature. The low-k dielectric feature may include two dissimilar dielectric layers, one of which may be air.
    Type: Application
    Filed: April 13, 2020
    Publication date: December 31, 2020
    Inventors: I-Hsieh Wong, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20200411530
    Abstract: A semiconductor device includes a first device disposed in an NMOS region of the semiconductor device. The first device includes a first gate-all-around (GAA) device having a vertical stack of nano-structure channels. The semiconductor device also includes a second device in a PMOS region of the semiconductor device. The second device includes a FinFET that includes a fin structure having a fin width. The fin structure is separated from an adjacent fin structure by a fin pitch. A maximum channel width of the nano-structure channels is no greater than a sum of: the fin width and the fin pitch. Alternatively, the second device includes a second GAA device having a different number of nano-structure channels than the first GAA device.
    Type: Application
    Filed: April 13, 2020
    Publication date: December 31, 2020
    Inventors: I-Hsieh Wong, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20200411328
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a first active region adjacent a channel, the channel, and a second active region adjacent the channel. The channel has a channel doping profile. The channel includes a central channel portion having a first dopant concentration of a first dopant and a radial channel portion surrounding the central channel portion. The radial channel portion has a second dopant concentration of a second dopant greater than the first dopant concentration. The channel comprising the central channel portion and the radial channel portion has increased voltage threshold tuning as compared to a channel that lacks a central channel portion and a radial channel portion.
    Type: Application
    Filed: September 14, 2020
    Publication date: December 31, 2020
    Inventors: Yen-Ting CHEN, I-Hsieh WONG, Chee-Wee LIU
  • Patent number: 10777426
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a first active region adjacent a channel, the channel, and a second active region adjacent the channel. The channel has a channel doping profile. The channel includes a central channel portion having a first dopant concentration of a first dopant and a radial channel portion surrounding the central channel portion. The radial channel portion has a second dopant concentration of a second dopant greater than the first dopant concentration. The channel comprising the central channel portion and the radial channel portion has increased voltage threshold tuning as compared to a channel that lacks a central channel portion and a radial channel portion.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yen-Ting Chen, I-Hsieh Wong, Chee-Wee Liu
  • Publication number: 20200176591
    Abstract: In an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.
    Type: Application
    Filed: April 12, 2019
    Publication date: June 4, 2020
    Inventors: I-Hsieh Wong, Yen-Ting Chen, Wei-Yang Lee, Feng-Cheng Yang, Yen-Ming Chen
  • Publication number: 20200105620
    Abstract: A method includes forming a first fin extending from a substrate, forming a first gate stack over and along sidewalls of the first fin, forming a first spacer along a sidewall of the first gate stack, the first spacer including a first composition of silicon oxycarbide, forming a second spacer along a sidewall of the first spacer, the second spacer including a second composition of silicon oxycarbide, forming a third spacer along a sidewall of the second spacer, the third spacer including silicon nitride, and forming a first epitaxial source/drain region in the first fin and adjacent the third spacer.
    Type: Application
    Filed: July 1, 2019
    Publication date: April 2, 2020
    Inventors: Wei-Chun Tan, I-Hsieh Wong, Te-En Cheng, Yung-Hui Lin, Wei-Ken Lin, Wei-Yang Lee, Chih-Hung Nien
  • Publication number: 20200098917
    Abstract: A method of manufacturing a semiconductor device includes forming an alloy semiconductor material layer comprising a first element and a second element on a semiconductor substrate. A mask is formed on the alloy semiconductor material layer to provide a masked portion and an unmasked portion of the alloy semiconductor material layer. The unmasked portion of the alloy semiconductor material layer not covered by the mask is irradiated with radiation from a radiation source to transform the alloy semiconductor material layer so that a surface region of the unmasked portion of the alloy semiconductor material layer has a higher concentration of the second element than an internal region of the unmasked portion of the alloy semiconductor material layer. The surface region surrounds the internal region.
    Type: Application
    Filed: November 18, 2019
    Publication date: March 26, 2020
    Inventors: Fang-Liang LU, I-Hsieh WONG, Shih-Ya LIN, Cheewee LIU, Samuel C. PAN
  • Patent number: 10510888
    Abstract: A method of manufacturing a semiconductor device includes forming an alloy semiconductor material layer comprising a first element and a second element on a semiconductor substrate. A mask is formed on the alloy semiconductor material layer to provide a masked portion and an unmasked portion of the alloy semiconductor material layer. The unmasked portion of the alloy semiconductor material layer not covered by the mask is irradiated with radiation from a radiation source to transform the alloy semiconductor material layer so that a surface region of the unmasked portion of the alloy semiconductor material layer has a higher concentration of the second element than an internal region of the unmasked portion of the alloy semiconductor material layer. The surface region surrounds the internal region.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: December 17, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Fang-Liang Lu, I-Hsieh Wong, Shih-Ya Lin, CheeWee Liu, Samuel C. Pan
  • Publication number: 20190326437
    Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 24, 2019
    Inventors: Huang-Siang LAN, CheeWee LIU, Chi-Wen LIU, Shih-Hsien HUANG, I-Hsieh WONG, Hung-Yu YEH, Chung-En TSAI
  • Publication number: 20190312132
    Abstract: A method of manufacturing a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers on a substrate. The first and second semiconductor layers include first end portions on either side of a second portion along a length of the first and second semiconductor layers. The first and second semiconductor layers are formed of different materials. The second portion of the first semiconductor layers is removed to form spaces. A mask layer is formed over the second portion of an uppermost second semiconductor layer above the spaces. The first portions of first and second semiconductor layers are irradiated with radiation from a radiation source to cause material from the first portions of the first and second semiconductor layers to combine with each other.
    Type: Application
    Filed: June 24, 2019
    Publication date: October 10, 2019
    Inventors: I-Hsieh WONG, Samuel C. PAN, Chee-Wee LIU, Huang-Siang LAN, Chung-En TSAI, Fang-Liang LU
  • Patent number: 10340383
    Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: July 2, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Huang-Siang Lan, CheeWee Liu, Chi-Wen Liu, Shih-Hsien Huang, I-Hsieh Wong, Hung-Yu Yeh, Chung-En Tsai
  • Patent number: 10332985
    Abstract: A method of manufacturing a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers on a substrate. The first and second semiconductor layers include first end portions on either side of a second portion along a length of the first and second semiconductor layers. The first and second semiconductor layers are formed of different materials. The second portion of the first semiconductor layers is removed to form spaces. A mask layer is formed over the second portion of an uppermost second semiconductor layer above the spaces. The first portions of first and second semiconductor layers are irradiated with radiation from a radiation source to cause material from the first portions of the first and second semiconductor layers to combine with each other.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: June 25, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: I-Hsieh Wong, Samuel C. Pan, Chee-Wee Liu, Huang-Siang Lan, Chung-En Tsai, Fang-Liang Lu
  • Publication number: 20190067456
    Abstract: A method of manufacturing a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers on a substrate. The first and second semiconductor layers include first end portions on either side of a second portion along a length of the first and second semiconductor layers. The first and second semiconductor layers are formed of different materials. The second portion of the first semiconductor layers is removed to form spaces. A mask layer is formed over the second portion of an uppermost second semiconductor layer above the spaces. The first portions of first and second semiconductor layers are irradiated with radiation from a radiation source to cause material from the first portions of the first and second semiconductor layers to combine with each other.
    Type: Application
    Filed: March 29, 2018
    Publication date: February 28, 2019
    Inventors: I-Hsieh WONG, Samuel C. PAN, Chee-Wee LIU, Huang-Siang LAN, Chung-En TSAI, Fang-Liang LU
  • Patent number: 10068995
    Abstract: In a method of fabricating a field effect transistor, a fin structure made of a first semiconductor material is formed so that the fin structure protrudes from an isolation insulating layer disposed over a substrate. A gate structure is formed over a part of the fin structure, thereby defining a channel region, a source region and a drain region in the fin structure. After the gate structure is formed, laser annealing is performed on the fin structure.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: September 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fang-Liang Lu, CheeWee Liu, Chi-Wen Liu, Shih-Hsien Huang, I-Hsieh Wong
  • Publication number: 20180151734
    Abstract: A method of manufacturing a semiconductor device includes forming an alloy semiconductor material layer comprising a first element and a second element on a semiconductor substrate. A mask is formed on the alloy semiconductor material layer to provide a masked portion and an unmasked portion of the alloy semiconductor material layer. The unmasked portion of the alloy semiconductor material layer not covered by the mask is irradiated with radiation from a radiation source to transform the alloy semiconductor material layer so that a surface region of the unmasked portion of the alloy semiconductor material layer has a higher concentration of the second element than an internal region of the unmasked portion of the alloy semiconductor material layer. The surface region surrounds the internal region.
    Type: Application
    Filed: July 7, 2017
    Publication date: May 31, 2018
    Inventors: Fang-Liang LU, I-Hsieh WONG, Shih-Ya LIN, CheeWee LIU, Samuel C. PAN
  • Publication number: 20180102258
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a first active region adjacent a channel, the channel, and a second active region adjacent the channel. The channel has a channel doping profile. The channel includes a central channel portion having a first dopant concentration of a first dopant and a radial channel portion surrounding the central channel portion. The radial channel portion has a second dopant concentration of a second dopant greater than the first dopant concentration. The channel comprising the central channel portion and the radial channel portion has increased voltage threshold tuning as compared to a channel that lacks a central channel portion and a radial channel portion.
    Type: Application
    Filed: December 13, 2017
    Publication date: April 12, 2018
    Inventors: Yen-Ting Chen, I-Hsieh Wong, Chee-Wee Liu
  • Patent number: 9923093
    Abstract: Semiconductor devices and methods of forming the same are provided. A first source/drain layer is formed over a substrate. A channel layer is formed over the first source/drain layer. A second source/drain layer is formed over the channel layer. The first source/drain layer, the channel layer, and the second source/drain layer are patterned to form a fin-shaped structure. A gate stack is formed on a sidewall of the fin-shaped structure. The fin-shaped structure is patterned to expose a top surface of the first source/drain layer.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: March 20, 2018
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Chee Wee Liu, Samuel C. Pan, I-Hsieh Wong, Hung-Yu Yeh