Patents by Inventor I-Hsuan Peng

I-Hsuan Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9859181
    Abstract: In some embodiments, a semiconductor device includes a first die, a second die coupled to a first surface of the first die, and a third die coupled to the first surface of the first die. The semiconductor device further includes an underfill material disposed between the first die and the second die and between the first die and the third die. A first volume of the underfill material for the second die is different than a second volume of the underfill material for the third die.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Szu-Wei Lu, I-Hsuan Peng
  • Publication number: 20170373038
    Abstract: A semiconductor package structure has a first electronic component on an insulating layer, a dielectric layer on the insulating layer and surrounding the first electronic component, a second electronic component stacked on the first electronic component, wherein an active surface of the first electronic component faces an active surface of the second electronic component, a molding compound on the first electronic component and surrounding the second electronic component, a third electronic component stacked on the second electronic component and the molding compound.
    Type: Application
    Filed: September 6, 2017
    Publication date: December 28, 2017
    Inventors: Tzu-Hung LIN, Ching-Wen HSIAO, I-Hsuan PENG
  • Publication number: 20170338175
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure. The RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace. The RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The extended wing portion overlaps at least one-half of a boundary of the symmetrical portion when observed from a plan view.
    Type: Application
    Filed: April 7, 2017
    Publication date: November 23, 2017
    Inventors: Nai-Wei LIU, Tzu-Hung LIN, I-Hsuan PENG, Che-Hung KUO, Che-Ya CHOU, Wei-Che HUANG
  • Patent number: 9786632
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first electronic component on a substrate. The semiconductor package structure also includes a second electronic component stacked on the first electronic component. The active surface of the first electronic component faces the active surface of the second electronic component. The semiconductor package structure further includes a molding compound on the first electronic component and surrounding the second electronic component. In addition, the semiconductor package structure includes a third electronic component stacked on the second electronic component and the molding compound.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: October 10, 2017
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Ching-Wen Hsiao, I-Hsuan Peng
  • Publication number: 20170287877
    Abstract: In one implementation, a semiconductor package assembly includes a semiconductor die, a first molding compound covering a back surface of the semiconductor die, a redistribution layer (RDL) structure disposed on a front surface of the semiconductor die, wherein the semiconductor die is coupled to the RDL structure, and a passive device, embedded in the redistribution layer (RDL) structure and coupled to the semiconductor die.
    Type: Application
    Filed: June 16, 2017
    Publication date: October 5, 2017
    Inventors: Tzu-Hung LIN, Ching-Wen HSIAO, I-Hsuan PENG
  • Publication number: 20170278832
    Abstract: In one implementation, a semiconductor package assembly includes a first semiconductor package having a first semiconductor die and a first redistribution layer (RDL) structure coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace at a first layer-level, a second conductive trace at a second layer-level, and a first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer , which is beside the first inter-metal dielectric (IMD) layer, wherein the second inter-metal dielectric (IMD) layer is disposed between the first conductive trace and the second conductive trace, and the second inter-metal dielectric (IMD) layer is zigzag shape in a cross-sectional view.
    Type: Application
    Filed: June 9, 2017
    Publication date: September 28, 2017
    Inventors: Tzu-Hung LIN, I-Hsuan PENG, Ching-Wen HSIAO
  • Publication number: 20170243826
    Abstract: A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die is disposed on and electrically coupled to the first surface of the first RDL structure. A first molding compound is disposed on the first surface of the first RDL structure and surrounds the first semiconductor die. A plurality of solder balls or conductive pillar structures is disposed in the first molding compound and electrically coupled to the first semiconductor die through the first RDL structure. A method for forming the semiconductor package is also provided.
    Type: Application
    Filed: January 30, 2017
    Publication date: August 24, 2017
    Inventors: Tzu-Hung LIN, I-Hsuan PENG, Ching-Wen HSIAO, Nai-Wei LIU, Wei-Che HUANG
  • Patent number: 9711488
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a semiconductor die. A first molding compound covers a back surface of the semiconductor die. A redistribution layer (RDL) structure is disposed on a front surface of the semiconductor die. The semiconductor die is coupled to the RDL structure. A second molding compound is disposed on the front surface of the semiconductor die and embedded in the RDL structure. A passive device is disposed on the second molding compound and coupled to the semiconductor die.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: July 18, 2017
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, Ching-Wen Hsiao, I-Hsuan Peng
  • Patent number: 9704836
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace disposed at a first layer-level. A second conductive trace is disposed at a second layer-level. A first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer, which is beside the first inter-metal dielectric (IMD) layer, are disposed between the first conductive trace and the second conductive trace.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: July 11, 2017
    Assignee: MEDIATEK INC.
    Inventors: Tzu-Hung Lin, I-Hsuan Peng, Ching-Wen Hsiao
  • Publication number: 20170141041
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The RDL structure includes a redistribution layer (RDL) contact pad arranged close to the second surface. A passivation layer is disposed on the RDL contact pad. The passivation layer has an opening corresponding to the RDL contact pad such that the RDL contact pad is exposed to the opening. A first distance between a first position of the opening and a central point of the opening is different from a second distance between a second position of the opening and the central point of the opening in a plan view.
    Type: Application
    Filed: October 31, 2016
    Publication date: May 18, 2017
    Inventors: Tzu-Hung LIN, Nai-Wei LIU, I-Hsuan PENG, Wei-Che HUANG
  • Publication number: 20170098629
    Abstract: A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.
    Type: Application
    Filed: July 25, 2016
    Publication date: April 6, 2017
    Inventors: Nai-Wei LIU, Tzu-Hung LIN, I-Hsuan PENG, Ching-Wen HSIAO, Wei-Che HUANG
  • Publication number: 20170098628
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor body and a conductive structure disposed below the semiconductor body. The semiconductor package structure also includes an insulating layer surrounding the conductive structure. The semiconductor package structure further includes a redistribution layer structure coupled to the conductive structure. In addition, the semiconductor package structure includes a molding compound surrounding the semiconductor body. A portion of the molding compound extends between the redistribution layer structure and the semiconductor body.
    Type: Application
    Filed: July 15, 2016
    Publication date: April 6, 2017
    Inventors: Nai-Wei LIU, Tzu-Hung LIN, I-Hsuan PENG, Ching-Wen HSIAO, Wei-Che HUANG
  • Publication number: 20170098589
    Abstract: A semiconductor package structure is provided. The structure includes a molding compound having a dicing lane region. A semiconductor die is disposed in the molding compound and surrounded by the dicing lane region. The semiconductor die has a first surface and a second surface opposite thereto, and the first and second surfaces are exposed from the molding compound. The structure further includes a redistribution layer (RDL) structure disposed on the first surface of the semiconductor die and covering the molding compound. The RDL structure includes a photo-sensitive material and has an opening aligned with the dicing lane region.
    Type: Application
    Filed: July 15, 2016
    Publication date: April 6, 2017
    Inventors: Nai-Wei LIU, Tzu-Hung LIN, I-Hsuan PENG, Ching-Wen HSIAO, Wei-Che HUANG
  • Publication number: 20170077073
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor package that includes a first semiconductor die having a first surface and a second surface opposite thereto. A first package substrate is disposed on the first surface of the first semiconductor die. A first molding compound surrounds the first semiconductor die and the first package substrate. A first redistribution layer (RDL) structure is disposed on the first molding compound, in which the first package substrate is interposed and electrically coupled between the first semiconductor die and the first RDL structure.
    Type: Application
    Filed: July 6, 2016
    Publication date: March 16, 2017
    Inventors: Tzu-Hung LIN, Chi-Chin LIEN, Nai-Wei LIU, I-Hsuan PENG, Ching-Wen HSIAO, Wei-Che HUANG
  • Publication number: 20170053884
    Abstract: A ball grid array for an integrated circuit package includes an array of connection points derived from a base unit of hexagonal pattern repeated in at least one or more sections of the integrated circuit package. According to one embodiment, the connection points are solder balls mounted on a lower surface of the integrated circuit package.
    Type: Application
    Filed: June 14, 2016
    Publication date: February 23, 2017
    Inventors: Tzu-Hung Lin, Ching-Wen Hsiao, I-Hsuan Peng, Nai-Wei Liu
  • Publication number: 20170040266
    Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces close to the first surface of the first RDL structure. An antenna pattern is disposed close to the second surface of the first RDL structure. A first semiconductor die is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.
    Type: Application
    Filed: October 21, 2016
    Publication date: February 9, 2017
    Inventors: Tzu-Hung LIN, I-Hsuan PENG, Nai-Wei LIU, Wei-Che HUANG, Che-Ya CHOU
  • Publication number: 20170033079
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first electronic component on a substrate. The semiconductor package structure also includes a second electronic component stacked on the first electronic component. The active surface of the first electronic component faces the active surface of the second electronic component. The semiconductor package structure further includes a molding compound on the first electronic component and surrounding the second electronic component. In addition, the semiconductor package structure includes a third electronic component stacked on the second electronic component and the molding compound.
    Type: Application
    Filed: June 16, 2016
    Publication date: February 2, 2017
    Inventors: Tzu-Hung LIN, Ching-Wen HSIAO, I-Hsuan PENG
  • Publication number: 20160343695
    Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die and includes a first conductive trace. The semiconductor package assembly also includes a second semiconductor package bonded to the first semiconductor package. The second semiconductor package includes a second semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. A second RDL structure is coupled to the second semiconductor die and includes a second conductive trace. The first conductive trace is in direct contact with the second conductive trace.
    Type: Application
    Filed: March 16, 2016
    Publication date: November 24, 2016
    Inventors: Tzu-Hung LIN, Ching-Wen HSIAO, I-Hsuan PENG
  • Publication number: 20160343694
    Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor package. The semiconductor package includes a semiconductor die. A redistribution layer (RDL) structure is disposed on the semiconductor die and is electrically connected to the semiconductor die. An active or passive element is disposed between the semiconductor die and the RDL structure. A molding compound surrounds the semiconductor die and the active or passive element.
    Type: Application
    Filed: March 10, 2016
    Publication date: November 24, 2016
    Inventors: Tzu-Hung LIN, I-Hsuan PENG, Ching-Wen HSIAO
  • Publication number: 20160343685
    Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die. The semiconductor package assembly also includes a second semiconductor package bonded to the first semiconductor package. The second semiconductor package includes a second semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. A second RDL structure is coupled to the second semiconductor die. The first RDL structure is positioned between the first semiconductor die and the second RDL structure.
    Type: Application
    Filed: March 16, 2016
    Publication date: November 24, 2016
    Inventors: Tzu-Hung LIN, Ching-Wen HSIAO, I-Hsuan PENG