Patents by Inventor I-Hsuan Peng

I-Hsuan Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070254399
    Abstract: A method for manufacturing a thin film transistor (“TFT”) device includes providing a substrate, forming a patterned first metal layer on the substrate, forming an insulating layer over the patterned first metal layer, forming an amorphous silicon layer over the insulating layer, forming a first polycrystalline silicon layer over the amorphous silicon layer, forming a second polycrystalline silicon layer over the first polycrystalline silicon layer, doping the second polycrystalline silicon layer to form a doped polycrystalline silicon layer, patterning the amorphous silicon layer, first polycrystalline silicon layer and doped polycrystalline silicon layer to form an active region layer for the TFT device, and forming a patterned second metal layer over the active region layer.
    Type: Application
    Filed: April 27, 2006
    Publication date: November 1, 2007
    Applicant: Industrial Technology Research Institute
    Inventors: Min WANG, I-Hsuan PENG, Te-Chi WONG, Liang-Tang WANG, Chin-Jen HUANG
  • Publication number: 20070207574
    Abstract: A double-gate thin-film transistor and a method for forming the same, using low-temperature poly-silicon formed by direct deposition on a substrate so as to simplify the manufacturing process and improve the electrical characteristics. The double-gate thin-film transistor comprises: a first patterned electrode formed on a substrate; a first dielectric layer; a poly-silicon film, formed by direct deposition on the first dielectric layer so as to form between the poly-silicon film and the first dielectric layer an incubation layer comprising amorphous silicon; a pair of second patterned electrodes, formed on the poly-silicon film so as to define in the poly-silicon film and the incubation layer between the second patterned electrodes a channel region corresponding to the first patterned electrode; a second dielectric layer; and a third patterned electrode corresponding to the channel region.
    Type: Application
    Filed: September 14, 2006
    Publication date: September 6, 2007
    Inventors: Liang-Tang Wang, Min-Chuang Wang, I-Hsuan Peng
  • Publication number: 20070195188
    Abstract: This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least one passive chip on the transparent substrate, wherein the photosensitive active area faces the transparent substrate; forming an insulating build-up film over the transparent substrate; and forming a plurality of conductive vias in the insulating build-up film wherein the ends of the conductive vias are connected with the passive chip or the first patterned conductive layer of the transparent substrate while the other ends of the conductive vias are exposed on the surface of the insulating build-up film. The packaging method is capable of down-sizing the construction of the image sensor module and simplifying the processing steps.
    Type: Application
    Filed: April 25, 2007
    Publication date: August 23, 2007
    Applicant: Industrial Technology Research Institute
    Inventors: Fang-Jun Leu, Shou-Lung Chen, Ching-Wen Hsiao, Shan-Pu Yu, Jyh-Rong Lin, I-Hsuan Peng, Jian-Shu Wu, Hui-Mei Wu, Chien-Wei Chieh
  • Publication number: 20070105373
    Abstract: A method for forming a polysilicon film in a plasma-assisted chemical vapor deposition (CVD) system including a chamber in which a first electrode and a second electrode spaced apart from the first electrode are provided comprises providing a substrate on the second electrode, the substrate including a surface exposed to the first electrode, applying a first power to the first electrode for generating a plasma in the chamber, applying a second power to the second electrode during a nucleation stage of the polysilicon film for ion bombarding the surface of the substrate, and flowing an erosive gas into the chamber.
    Type: Application
    Filed: November 9, 2005
    Publication date: May 10, 2007
    Inventors: Liang-Tang Wang, Chi-Lin Chen, I-Hsuan Peng, Jung-Fang Chang, Chin-Jen Huang
  • Publication number: 20070077735
    Abstract: A low temperature poly-silicon thin film element, method of making poly-silicon thin film by direct deposition at low temperature, and the inductively-coupled plasma chemical vapor deposition equipment utilized, wherein the poly-silicon material is induced to crystallize into a poly-silicon thin film at low temperature by means of high density plasma and substrate bias voltage. Furthermore, the atom structure of the poly-silicon thin film is aligned in regular arrangement by making use of the induction layer having optimal orientation and lattice constant close to that of the silicon, thus raising the crystallization quality of the poly-silicon thin film and reducing the thickness of the incubation layer.
    Type: Application
    Filed: April 3, 2006
    Publication date: April 5, 2007
    Inventors: I-Hsuan Peng, Chin-Jen Huang, Liang-Tang Wang, Jung-Fang Chang, Te-Chi Wong
  • Publication number: 20060220212
    Abstract: A stacked package for electronic elements is provided, a plurality of stud bumps are formed on a substrate by means of a stud bump process to align with a plurality of vias of one provided electronic element. The stud bumps respectively pass through the vias and electrically connect the electronic element. Furthermore, additional electronic elements are stacked on the carrier according to a similar way to form a stacked electronic package.
    Type: Application
    Filed: June 5, 2006
    Publication date: October 5, 2006
    Inventors: Shou-Lung Chen, Fang-Jun Leu, I-Hsuan Peng, Shan-Pu Yu
  • Patent number: 7091592
    Abstract: A stacked package for electronic elements is provided, a plurality of stud bumps are formed on a substrate by means of a stud bump process to align with a plurality of vias of one provided electronic element. The stud bumps respectively pass through the vias and electrically connect the electronic element. Furthermore, additional electronic elements are stacked on the carrier according to a similar way to form a stacked electronic package.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: August 15, 2006
    Assignee: Industrial Technology Research Institute
    Inventors: Shou-Lung Chen, Fang-Jun Leu, I-Hsuan Peng, Shan-Pu Yu
  • Publication number: 20060030070
    Abstract: This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least one passive chip on the transparent substrate, wherein the photosensitive active area faces the transparent substrate; forming an insulating build-up film over the transparent substrate; and forming a plurality of conductive vias in the insulating build-up film wherein the ends of the conductive vias are connected with the passive chip or the first patterned conductive layer of the transparent substrate while the other ends of the conductive vias are exposed on the surface of the insulating build-up film. The packaging method is capable of down-sizing the construction of the image sensor module and simplifying the processing steps.
    Type: Application
    Filed: August 2, 2005
    Publication date: February 9, 2006
    Applicant: Industrial Technology Research Institute
    Inventors: Fang-Jun Leu, Shou-Lung Chen, Ching-Wen Hsiao, Shan-Pu Yu, Jyh-Rong Lin, I-Hsuan Peng, Jian-Shu Wu, Hui-Mei Wu, Chien-Wei Chieh
  • Publication number: 20040238933
    Abstract: A stacked package for electronic elements is provided, a plurality of stud bumps are formed on a substrate by means of a stud bump process to align with a plurality of vias of one provided electronic element. The stud bumps respectively pass through the vias and electrically connect the electronic element. Furthermore, additional electronic elements are stacked on the carrier according to a similar way to form a stacked electronic package.
    Type: Application
    Filed: February 19, 2004
    Publication date: December 2, 2004
    Inventors: Shou-Lung Chen, Fang-Jun Leu, I-Hsuan Peng, Shan-Pu Yu