Abstract: A gate-all-around structure is provided. The gate-all-around structure includes a plurality of nanostructures stacked over a substrate in a vertically direction, and the nanostructures extends from a gate region to a source/drain (S/D) region. The gate-all-around structure includes a gate structure formed in the gate region around the first nanostructures, and a S/D structure formed in the S/D region. The S/D structure is in direct contact with a top surface of one of the nanostructures.

Abstract: The present disclosure describes a method that includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite to the first sidewall. The method also includes depositing a shallow-trench isolation (STI) material on the substrate. Depositing the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method also includes performing a first etching process on the STI material to etch the first portion of the STI material at a first etching rate and the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material to etch the first portion of the STI material at a third etching rate and the second portion of the STI material at a fourth etching rate less than the third etching rate.

Abstract: A semiconductor substrate includes a first material layer made of a first material and including a plurality of protrusions, and a second material layer made of a second material different from the first material, filling spaces between the plurality of protrusions, and covering the plurality of protrusions. Each of the protrusions includes a tip and a plurality of facets converging at the tip, and adjacent facets of adjacent protrusions are in contact with each other.

Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.

Abstract: The present disclosure describes a method that includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite to the first sidewall. The method also includes depositing a shallow-trench isolation (STI) material on the substrate. Depositing the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method also includes performing a first etching process on the STI material to etch the first portion of the STI material at a first etching rate and the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material to etch the first portion of the STI material at a third etching rate and the second portion of the STI material at a fourth etching rate less than the third etching rate.

Abstract: An energy storage device includes a sensor, a communication circuit and a processor. The sensor is configured to detect an abnormal event occurred in the energy storage device. The communication circuit is configured to connect to a local area network. The local area network includes a plurality of nodes formed by the energy storage device and other energy storage devices. The processor is configured to generate, according to the abnormal event detected by the sensor, historical usage data recording the abnormal event. In response to a trigger event, the processor is further configured to: update the historical usage data; and control the communication circuit to transmit at least part of the updated historical usage data to at least one energy storage device adjacent to the energy storage device in the local area network.

Abstract: A multi-gate semiconductor device includes a plurality of nanostructures vertically stacked over a substrate, a gate dielectric layer wrapping around the plurality of nanostructures, a gate conductive structure over the gate dielectric layer, and a first insulating spacer alongside the gate conductive structure and over the plurality of nanostructures. The first insulating spacer is in direct contact with the gate conductive structure and the gate dielectric layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a fin structure over the substrate. The fin structure has a channel height. The semiconductor device structure also includes a stack of nanostructures over the substrate. The channel height is greater than a lateral distance between the fin structure and the stack of the nanostructures. The semiconductor device structure further includes a metal gate stack over the nanostructures, and the nanostructures are separated from each other by portions of the metal gate stack. In addition, the semiconductor device structure includes a dielectric layer surrounding the metal gate stack, the nanostructures, and the fin structure.

Abstract: A method includes: providing a first gate electrode over the substrate; forming a first pair of spacers on two sides of the first gate electrode; removing the first gate electrode to form a first trench between the first pair of spacers; depositing a dielectric layer in the first trench; depositing a first layer over the dielectric layer; removing the first layer from the first trench; and depositing a work function layer over the dielectric layer in the first trench.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers.

Abstract: A method for forming a multi-gate semiconductor device includes forming a fin structure including alternating stacked first semiconductor layers and second semiconductor layers over a substrate, forming a dummy gate structure across the fin structure, forming a first spacer alongside the dummy gate structure, removing a first portion of the first spacer to expose the dummy gate structure, forming a second spacer between a second portion of first spacer and the dummy gate structure after removing the first portion of the first spacer, removing the dummy gate structure to expose a sidewall of the second spacer, removing the first semiconductor layers of the fin structure to form a plurality of nanostructures from the second semiconductor layers of the fin structure, and forming a gate conductive structure to wrap around the plurality of nanostructures. The gate conductive structure is in contact with the sidewall of the second spacer.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. A sacrificial gate layer is removed to form a gate trench exposing a sacrificial dielectric layer. An ion implantation is performed to a portion of a substrate covered by the sacrificial dielectric layer in the gate trench. The sacrificial dielectric layer is removed to expose the substrate from the gate trench. An interfacial layer is formed over the substrate in the gate trench. A metal gate structure is formed over the interfacial layer in the gate trench.

Abstract: A distance determination method has: detecting a first received signal strength indicator (RSSI) of a first electronic device by a second electronic device; detecting a second RSSI of the second electronic device by the first electronic device; obtaining the first RSSI from the second electronic device by the first electronic device; and calculating a motion direction and a distance of the second electronic device relative to the first electronic device according to the first RSSI and the second RSSI by the first electronic device.

Abstract: A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.

Abstract: A structure and a formation method of hybrid semiconductor devices are provided. The structure includes a substrate and a fin structure over the substrate. The fin structure has a channel height. The structure also includes a stack of nanostructures over the substrate. The channel height is greater than a lateral distance between the fin structure and the stack of the nanostructures. The structure further includes a gate stack over the nanostructures. The nanostructures are separated from each other by portions of the gate stack.

Abstract: A method includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; performing an operation on the substrate; removing the barrier layer from the first trench to expose the dielectric layer subsequent to the operation; and depositing a work function layer over the dielectric layer in the first trench.

Abstract: The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure.

Abstract: A semiconductor substrate includes a first material layer made of a first material and including a plurality of protrusions, and a second material layer made of a second material different from the first material, filling spaces between the plurality of protrusions, and covering the plurality of protrusions.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and multiple nanostructures over the substrate. The semiconductor device structure also includes a semiconductor fin between the substrate and the nanostructures. The semiconductor device structure further includes a gate stack wrapped around the nanostructures. The gate stack includes a gate dielectric layer, and the gate dielectric layer continuously extends along a bottommost nanostructure of the nanostructures and an upper portion of the semiconductor fin.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation layer formed over a substrate, and a plurality of nanostructures formed over the isolation layer. The semiconductor device structure includes a gate structure wrapped around the nanostructures, and an S/D structure wrapped around the nanostructures. The semiconductor device structure also includes a first oxide layer between the substrate and the S/D structure. The first oxide layer and the isolation layer are made of different materials, and the first oxide layer is in direct contact with the isolation layer, and a sidewall surface of the S/D structure is aligned with a sidewall surface of the first oxide layer.