Abstract: A current detection equipment comprises a first coil and a second coil connected in series with the first coil. The current detection equipment is capable of detecting a current flowing through an object which is provided between the first and second coils or provided in a vicinity of the first or second coil. Each of the first and second coils having first conductive patterns provided on a surface of a substrate, a second conductive patterns provided on a back of the substrate and connecting parts which connect the first and second conductive patterns. A semiconductor device including the current detection equipment to measure the current flowing in a semiconductor element is also proposed.

Abstract: A gate driving circuit and method which increases the switching frequency by use of a switching control circuit which controls operations of a first, second, third, and fourth switches. The switching control circuit performs switching control of a power MOSFET when the MOSFET is to be turned on, so that a period exists when the first and fourth switches are simultaneously ON. The switching circuit also performs switching control when a MOSFET is to be turned off, so that a period exists when the second and third switches are simultaneously ON.

Abstract: A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.

Abstract: A semiconductor device is disclosed, which comprises a terminal section formed to surround a device active region. The terminal section includes a trench formed in the semiconductor layer, and a filler filled in the trench. A field plate is extended to above the trench from an electrode of the semiconductor element formed in the device active region.

Abstract: A nitride semiconductor device according to one embodiment of the present invention comprises: a non-doped first aluminum gallium nitride (AlxGa1-xN (0?x?1)) layer which is formed as a channel layer; a non-doped or n type second aluminum gallium nitride (AlyGa1-yN (0?x?1,x<y)) layer which is formed on the first aluminum gallium nitride layer as a barrier layer; an aluminum nitride (AlN) film which is formed on the second aluminum gallium nitride layer as a gate insulating film lower layer; an aluminum oxide (Al2O3) film which is formed on the aluminum nitride film as a gate insulating film upper layer; a source electrode and a drain electrode which are formed as first and second main electrodes to be electrically connected to the second aluminum gallium nitride layer, respectively; and a gate electrode which is formed on the aluminum oxide film as a control electrode.

Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Abstract: The power semiconductor device according to one embodiment of the present invention at least comprises: first pillar layers of the first conductive type and second pillar layers of a second conductive type which constitute a super-junction structure in a device section and which are arranged alternately in a horizontal direction, each of the first and second pillar layers having a column-shaped sectional structure; third pillar layers of the first conductive type and fourth pillar layers of the second conductive type which are adjacent to the super-junction structure of the device section to constitute another super-junction structure thinner in a vertical direction than the super-junction structure of the device section in a device termination section and which are arranged alternately in a horizontal direction, each of the third and fourth pillar layers having a column-shaped sectional structure; an outermost pillar layer which is stacked on one of the third or fourth pillar layers in the super-junction str

Abstract: The nitride semiconductor device according to one embodiment of the present invention comprises: a silicon substrate; a first aluminum gallium nitride (AlxGa1-xN (0?x?1)) layer formed as a channel layer on the silicon substrate in an island shape; and a second aluminum gallium nitride (AlyGa1-yN (0?y?1, x?y)) layer formed as a barrier layer of a first conductive type or i-type on the first aluminum gallium nitride layer.

Abstract: A power semiconductor device includes a first semiconductor layer, a second semiconductor layer of a first conductivity type, first and second main electrodes, a control electrode and a third semi-conductor layer. The second semiconductor layer is formed on the first semiconductor layer. The first and second main electrodes are formed on the second semiconductor layer separately from each other. The control electrode is formed on the second semiconductor layer between the first and second main electrodes. The third semiconductor layer is formed on the second semiconductor layer between the control electrode and the second main electrode.

Abstract: There are provided a power switching element including a first semiconductor layer of a first conductivity type; a plurality of second semiconductor layers of a second conductivity type, which are in a columnar shape, and arranged in the first semiconductor layer at certain intervals in a direction parallel to a layer surface of the first semiconductor layer; a first electrode formed on a surface of one side of the first semiconductor layer, the first electrode being electrically connected with the first semiconductor layer; a plurality of third semiconductor layers selectively formed in a surface region of the other side of the first semiconductor layer, the third semiconductor layers being connected to the second semiconductor layers; a fourth semiconductor layer of the first conductivity type selectively formed in a surface region of the third semiconductor layers; second electrodes formed so as to contact surfaces of the third semiconductor layers and the fourth semiconductor layer; and gate electrodes fo

Abstract: A power semiconductor device package according to one aspect of the present invention comprises: a plurality of power semiconductor chips which are arranged in a laminated structure so that the plurality of power semiconductor chips are opposing to each other at the surfaces with the same electrical structures, and which are connected in parallel to one another, and are sealed in a sealing resin as one body.

Abstract: A power semiconductor device includes a first semiconductor layer, a second semiconductor layer of a first conductivity type, first and second main electrodes, a control electrode and a third semiconductor layer. The second semiconductor layer is formed on the first semiconductor layer. The first and second main electrodes are formed on the second semiconductor layer separately from each other. The control electrode is formed on the second semiconductor layer between the first and second main electrodes. The third semiconductor layer is formed on the second semiconductor layer between the control electrode and the second main electrode.

Abstract: A semiconductor device includes: a first semiconductor layer represented by a composition formula AlxGa1-xN(0?x?1); a first conductivity type or non-doped second semiconductor layer represented by a composition formula AlyGa1-yN (0?y?1, x<y) and is formed on the first semiconductor layer; a second conductivity type third semiconductor layer represented by a composition formula AlxGa1-xN (0?x?1) and is selectively formed on the second semiconductor layer; a gate electrode formed on the third semiconductor layer; a source electrode electrically connected to the second semiconductor layer; and a drain electrode electrically connected to the second semiconductor layer; wherein the distance between the drain electrode and the third semiconductor layer is longer than the distance between the source electrode and the third semiconductor layer.

Abstract: A power semiconductor device including a non-doped GaN channel layer, an n-type Al0.2Ga0.8N barrier layer formed on the channel layer, a p-type Al0.1Ga0.9N semiconductor layer selectively formed on the barrier layer, a drain electrode positioned at one of both sides of the semiconductor layer and formed on the barrier layer, an insulating film formed on the barrier layer adjacent to the semiconductor layer between at least semiconductor layer and drain electrode, and a field plate electrode formed on the insulating film.

Abstract: An insulated gate semiconductor device includes a control electrode having a trench type structure formed on the surface of a first semiconductor layer of a first conductivity type via a gate insulation film and disposed in a lattice shape, the control electrode having a plurality of first control electrode sections and a plurality of second control electrode sections which intersect with the plurality of first control electrode sections, respectively, and a plurality of fifth semiconductor layers of a second conductivity type which are provided on an interface of the first semiconductor layer in contact with the plurality of second control electrode sections, and connected to at least one of a plurality of second semiconductor layers of the second conductivity type, the fifth semiconductor layers having impurity concentration lower than that of the plurality of second semiconductor layers.

Abstract: A semiconductor device including a drain layer having a first conductivity type, a drift layer having the first conductivity type, which is formed on the drain layer and has an impurity concentration lower than that in the drain layer, and a RESURF layer having a second conductivity type and formed to extend from a surface of the drift layer into the drain layer, the RESURF layer forming a superjunction structure together with the drift layer and forming a depletion layer in the drift layer.

Abstract: A power semiconductor device including a non-doped GaN channel layer, an n-type Al0.2Ga0.8N barrier layer formed on the channel layer, a p-type Al0.1Ga0.9N semiconductor layer selectively formed on the barrier layer, a drain electrode positioned at one of both sides of the semiconductor layer and formed on the barrier layer, an insulating film formed on the barrier layer adjacent to the semiconductor layer between at least semiconductor layer and drain electrode, and a field plate electrode formed on the insulating film.

Abstract: A method of manufacturing a semiconductor device in which a trench groove is formed in a first conductivity type semiconductor layer, and a second conductivity type semiconductor layer is epitaxially grown so as to bury the trench groove. The second conductivity type semiconductor layer is then removed until a surface of the first conductivity type semiconductor layer is exposed. The first conductivity type semiconductor layer is epitaxially grown on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer such that the thickness of the first conductivity type semiconductor layer increases by a length which is substantially the same as a depth of the trench groove.

Abstract: A power semiconductor device is disclosed, which comprises a semiconductor layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, which are periodically formed in the lateral direction, and a power semiconductor element including the semiconductor layers that are formed periodically, wherein a distribution of an amount of an impurity in a vertical direction of the first semiconductor layer differs from a distribution of an amount of an impurity in the vertical direction of the second semiconductor layer.

Abstract: A power semiconductor device includes a first semiconductor layer, a second semiconductor layer of a first conductivity type, first and second main electrodes, a control electrode and a third semi-conductor layer. The second semiconductor layer is formed on the first semiconductor layer. The first and second main electrodes are formed on the second semiconductor layer separately from each other. The control electrode is formed on the second semiconductor layer between the first and second main electrodes. The third semiconductor layer is formed on the second semiconductor layer between the control electrode and the second main electrode.