Patents by Inventor Ido Ouziel

Ido Ouziel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160180079
    Abstract: A method comprises filtering branch trap events at a branch event filter, monitoring a branch event filter to capture indirect branch trap events that cause a control flow trap exception, receiving the indirect branch trap events at a handler and the handler processing the indirect branch trap events
    Type: Application
    Filed: December 19, 2014
    Publication date: June 23, 2016
    Inventors: Ravi L. Sahita, Xiaoning Li, Barry E. Huntley, Ofer Levy, Vedvyas Shanbhogue, Yuriy Bulygin, Ido Ouziel, Michael Lemay, John M. Esper
  • Patent number: 9335943
    Abstract: An apparatus and method for fine grain memory protection. For example, one embodiment of a method comprises: performing a first lookup operation using a virtual address to identify a physical address of a memory page, the memory page comprising a plurality of sub-pages; determining whether sub-page permissions are enabled for the memory page; if sub-page permissions are enabled, then performing a second lookup operation to determine permissions associated with one or more of the sub-pages of the memory page; and implementing the permissions associated with the one or more sub-pages.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 10, 2016
    Assignee: INTEL CORPORATION
    Inventors: Ravi L. Sahita, Vedvyas Shanbhogue, Gilbert Neiger, Jonathan Edwards, Ido Ouziel, Barry E. Huntley, Stanislav Shwartsman, David M. Durham, Andrew V. Anderson, Michael Lemay
  • Publication number: 20150378930
    Abstract: Systems and methods for validating virtual address translation. An example processing system comprises: a processing core to execute a first application associated with a first privilege level and a second application associated with a second privilege level, wherein a first set of privileges associated with the first privilege level includes a second set of privileges associated with the second privilege level; and an address validation component to validate, in view of an address translation data structure maintained by the first application, a mapping of a first address defined in a first address space of the second application to a second address defined in a second address space of the second application.
    Type: Application
    Filed: June 27, 2014
    Publication date: December 31, 2015
    Inventors: RAVI L. SAHITA, GILBERT NEIGER, DAVID M. DURHAM, VEDVYAS SHANBHOGUE, MICHAEL LEMAY, IDO OUZIEL, STANISLAV SHWARTSMAN, BARRY HUNTLEY, ANDREW V. ANDERSON
  • Publication number: 20150378633
    Abstract: An apparatus and method for fine grain memory protection. For example, one embodiment of a method comprises: performing a first lookup operation using a virtual address to identify a physical address of a memory page, the memory page comprising a plurality of sub-pages; determining whether sub-page permissions are enabled for the memory page; if sub-page permissions are enabled, then performing a second lookup operation to determine permissions associated with one or more of the sub-pages of the memory page; and implementing the permissions associated with the one or more sub-pages.
    Type: Application
    Filed: June 30, 2014
    Publication date: December 31, 2015
    Inventors: RAVI L. SAHITA, VEDVYAS SHANBHOGUE, GILBERT NEIGER, JONATHAN EDWARDS, IDO OUZIEL, BARRY E. HUNTLEY, STANISLAV SHWARTSMAN, DAVID M. DURHAM, ANDREW V. ANDERSON, MICHAEL LEMAY
  • Patent number: 8782374
    Abstract: Methods and apparatus for inclusion of TLB (translation look-aside buffer) in processor micro-op caches are disclosed. Some embodiments for inclusion of TLB entries have micro-op cache inclusion fields, which are set responsive to accessing the TLB entry. Inclusion logic may the flush the micro-op cache or portions of the micro-op cache and clear corresponding inclusion fields responsive to a replacement or invalidation of a TLB entry whenever its associated inclusion field had been set. Front-end processor state may also be cleared and instructions refetched when replacement resulted from a TLB miss.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: July 15, 2014
    Assignee: Intel Corporation
    Inventors: Lihu Rappoport, Chen Koren, Franck Sala, Oded Lempel, Ido Ouziel, Ron Gabor, Gregory Pribush, Lior Libis
  • Patent number: 8127085
    Abstract: Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: February 28, 2012
    Assignee: Intel Corporation
    Inventors: Lihu Rappoport, Chen Koren, Franck Sala, Oded Lempel, Ido Ouziel, Ilhyun Kim, Ron Gabor, Lior Libis, Gregory Pribush
  • Patent number: 8103831
    Abstract: Methods and apparatus for using micro-op caches in processors are disclosed. A tag match for an instruction pointer retrieves a set of micro-op cache line access tuples having matching tags. The set is stored in a match queue. Line access tuples from the match queue are used to access cache lines in a micro-op cache data array to supply a micro-op queue. On a micro-op cache miss, a macroinstruction translation engine (MITE) decodes macroinstructions to supply the micro-op queue. Instruction pointers are stored in a miss queue for fetching macroinstructions from the MITE. The MITE may be disabled to conserve power when the miss queue is empty-likewise for the micro-op cache data array when the match queue is empty. Synchronization flags in the last micro-op from the micro-op cache on a subsequent micro-op cache miss indicate where micro-ops from the MITE merge with micro-ops from the micro-op cache.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: January 24, 2012
    Assignee: Intel Corporation
    Inventors: Lihu Rappoport, Bob Valentine, Stephan Jourdan, Yoav Almog, Franck Sala, Amir Leibovitz, Ido Ouziel, Ron Gabor
  • Patent number: 8082430
    Abstract: A micro-operation (uop) fusion technique. More particularly, embodiments of the invention relate to a technique to fuse two or more uops originating from two or more instructions.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: December 20, 2011
    Assignee: Intel Corporation
    Inventors: Robert Valentine, Ittai Anati, Zeev Sperber, Ido Ouziel, Gregory Pribush, Amir Leibovitz
  • Publication number: 20100138608
    Abstract: Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache.
    Type: Application
    Filed: December 31, 2008
    Publication date: June 3, 2010
    Inventors: Lihu Rappoport, Chen Koren, Franck Sala, Oded Lempel, Ido Ouziel, Ilhyun Kim, Ron Gabor, Lior Libis, Gregory Pribush
  • Publication number: 20100138610
    Abstract: Methods and apparatus for inclusion of TLB (translation look-aside buffer) in processor micro-op caches are disclosed. Some embodiments for inclusion of TLB entries have micro-op cache inclusion fields, which are set responsive to accessing the TLB entry. Inclusion logic may the flush the micro-op cache or portions of the micro-op cache and clear corresponding inclusion fields responsive to a replacement or invalidation of a TLB entry whenever its associated inclusion field had been set. Front-end processor state may also be cleared and instructions refetched when replacement resulted from a TLB miss.
    Type: Application
    Filed: December 2, 2008
    Publication date: June 3, 2010
    Inventors: Lihu Rappoport, Chen Koren, Franck Sala, Oded Lempel, Ido Ouziel, Ron Gabor, Gregory Pribush, Lior Libis
  • Publication number: 20100115248
    Abstract: A technique to enable efficient instruction fusion within a computer system. In one embodiment, a processor logic delays the processing of a second instruction for a threshold amount of time if a first instruction within an instruction queue is fusible with the second instruction.
    Type: Application
    Filed: October 30, 2008
    Publication date: May 6, 2010
    Inventors: Ido Ouziel, Lihu Rappoport, Robert Valentine, Ron Gabor, Pankaj Raghuvanshi
  • Publication number: 20090249036
    Abstract: Methods and apparatus for using micro-op caches in processors are disclosed. A tag match for an instruction pointer retrieves a set of micro-op cache line access tuples having matching tags. The set is stored in a match queue. Line access tuples from the match queue are used to access cache lines in a micro-op cache data array to supply a micro-op queue. On a micro-op cache miss, a macroinstruction translation engine (MITE) decodes macroinstructions to supply the micro-op queue. Instruction pointers are stored in a miss queue for fetching macroinstructions from the MITE. The MITE may be disabled to conserve power when the miss queue is empty-likewise for the micro-op cache data array when the match queue is empty. Synchronization flags in the last micro-op from the micro-op cache on a subsequent micro-op cache miss indicate where micro-ops from the MITE merge with micro-ops from the micro-op cache.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 1, 2009
    Inventors: Lihu Rappoport, Robert Valentine, Stephan Jourdan, Franck Sala, Amir Leibovitz, Ido Ouziel, Ron Gabor