Abstract: An integrated circuit (IC) may include a scheduler for hardware acceleration. The scheduler may include a command queue having a plurality of slots and configured to store commands offloaded from a host processor for execution by compute units of the IC. The scheduler may include a status register having bit locations corresponding to the slots of the command queue. The scheduler may also include a controller coupled to the command queue and the status register. The controller may be configured to schedule the compute units of the IC to execute the commands stored in the slots of the command queue and update the bit locations of the status register to indicate which commands from the command queue are finished executing.

Abstract: An integrated circuit (IC) can include a command queue having a plurality of slots corresponding to commands from a host processor for execution by a plurality of compute units of the IC and a command request register having a plurality of locations corresponding to the plurality of slots in the command queue. The command request register is configured to generate an interrupt indicating a new command stored within the command queue. The IC can include a controller configured to, in response to the interrupt from the command request register, determine a selected compute unit that is idle from the plurality of compute units to execute the new command. The IC can also include a compute unit direct memory access circuit configured to provide the new command to the available compute unit.

Abstract: An integrated circuit (IC) can include a command queue having a plurality of slots corresponding to commands from a host processor for execution by a plurality of compute units of the IC and a command request register having a plurality of locations corresponding to the plurality of slots in the command queue. The command request register is configured to generate an interrupt indicating a new command stored within the command queue. The IC can include a controller configured to, in response to the interrupt from the command request register, determine a selected compute unit that is idle from the plurality of compute units to execute the new command. The IC can also include a compute unit direct memory access circuit configured to provide the new command to the available compute unit.

Abstract: An integrated circuit (IC) may include a scheduler for hardware acceleration. The scheduler may include a command queue having a plurality of slots and configured to store commands offloaded from a host processor for execution by compute units of the IC. The scheduler may include a status register having bit locations corresponding to the slots of the command queue. The scheduler may also include a controller coupled to the command queue and the status register. The controller may be configured to schedule the compute units of the IC to execute the commands stored in the slots of the command queue and update the bit locations of the status register to indicate which commands from the command queue are finished executing.