Abstract: Embodiments relate to systems methods and computer readable media to enable a wireless communication device are described. In one embodiment a wireless communication device is configured for phased array communications. The wireless communication device comprises radar circuitry to detect objects that scatter a transmit radiated signal from the wireless communication device. Control circuitry is used to adjust the transmit radiated power of the phased array communications based on information provided by the radar circuitry.

Abstract: Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by a delay. Gate circuitry generates a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired delay.

Abstract: An apparatus for regulating a supply voltage supplied from a voltage source to a load via a supply line is provided. The apparatus includes a control circuit configured to generate a control signal based on a difference between a value of the supply voltage and a nominal value of the supply voltage. Further, the apparatus includes a switch circuit configured to couple a charged capacitive element to the supply line based on the control signal.

Abstract: Techniques are disclosed implementing a radio partitioning architecture using multiple data streams over a single coaxial cable that does not require external RF filtering. This provides a flexible frequency scheme (e.g., using IF frequency adjustment) that enables the avoidance of Wi-Fi and LTE harmonics. The techniques include leveraging baseband filtering, which may be integrated with the radio head in a common radio frequency intergraded circuit (RFIC).

Abstract: Methods and architectures for closed loop digital pre-distortion (DPD) in a multi-stream phased array communication system include sampling outputs, from transmit antennas or dedicated analog detectors, of a plurality of RF power amplifiers operating in transmission of multi-stream transmission, correcting or normalizing the detected outputs, summing the outputs into a combined DPD feedback signal and selecting pre-distortion vectors to be used in altering the output of the PAs.

Abstract: An apparatus of a wireless communication device can include radar circuitry and communication circuitry. The radar circuitry can perform one or more proximity measurements. The radar circuitry can detect whether an object is near the apparatus that may affect one or more beamforming scanning operations or affect one or more communication of the apparatus utilizing the one or more beamforming scanning operations based on the one or more proximity measurements. The communication apparatus can adjust one or more beamforming scanning operations based on the one or more proximity measurements and perform the adjusted one or more beamforming scanning operations to reduce beamforming scanning time and/or scanning resources.

Abstract: A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.

Abstract: Systems, methods, and circuitries are disclosed for controlling an adaptive time-to-digital converter (TDC) that determines a phase difference between a reference signal and a phase locked loop (PLL) feedback signal. Adaptive TDC circuitry includes a chain of n delay elements each characterized by an incremental delay. Gate circuitry outputs a gated PLL feedback signal while a gating enable signal has an enable value. N sampling elements, each associated with a delay element, are enabled by the reference signal arriving at the input of the associated delay element to store a value of the gated PLL feedback signal. Adaptive gating circuitry is configured to generate the gating enable signal based on the incremental delay and a period of the PLL feedback signal. A supply voltage for the delay elements may be controlled to cause the delay elements to exhibit a desired incremental delay.

Abstract: An advanced split microwave architecture is provided. The advanced split microwave architecture includes a smart outdoor communication unit including a digital N-Plexer configured to multiplex and/or demultiplex a received data signal in the digital domain, a processor unit configured to carry out instructions to control operation of the digital N-Plexer, and a converter module configured to convert the received data signal between the digital domain and the analog domain. The smart outdoor communication unit further includes an RF module, having digital capabilities, configured to correct errors within the received data signal in the digital domain, perform a conversion of the received data signal, to amplify a power of the received data signal, and to perform automatic gain control in the digital domain.

Abstract: A point-to-point (PtP) communication system includes a near end antenna device configured to transmit a narrow antenna beam over a wireless link, and includes a far end antenna device configured receive the narrow antenna beam over the wireless link. The near end antenna device including a directive element configured to focus an electrical field into the narrow antenna beam, and including a beam steering element (e.g., a phased array feeder (PAF) assembly) configured to generate the electrical field and to track the far end antenna, and further including a communication interface unit (e.g., an outdoor unit) configured to perform operations on a transmitted signal and a received signal.

Abstract: Provided is a wound dressing prepared from whole blood that is clotted ex vivo to form a sheet of clotted blood that is applied onto the skin over a sight of skin injury.

Abstract: Control circuitry for use in generating a local oscillator (LO) signal is provided. Synthesizer control circuitry is configured to control synthesizer circuity to generate an analog oscillator signal having a first frequency at which phase noise is minimized. DS control circuitry is configured to generate a control word or message to cause DS circuitry to generate a digital DS signal having a desired frequency when the DS circuitry is clocked by the oscillator signal having the first frequency. The desired frequency is proportional to the LO signal frequency. The digital DS signal generated by the DS circuitry is used to generate the LO signal. Thus the first frequency used to clock the DS circuitry is selected to optimize the oscillator rather than having some relationship to the LO frequency. In addition, a single synthesizer may be used in order to simultaneously generate many LO signals.

Abstract: A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.

Abstract: A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.

Abstract: Control circuitry for use in generating a local oscillator (LO) signal is provided. Synthesizer control circuitry is configured to control synthesizer circuitry to generate an analog oscillator signal having a first frequency at which phase noise is minimized. DS control circuitry is configured to generate a control word or message to cause DS circuitry to generate a digital DS signal having a desired frequency when the DS circuitry is clocked by the oscillator signal having the first frequency. The desired frequency is proportional to the LO signal frequency. The digital DS signal generated by the DS circuitry is used to generate the LO signal. Thus the first frequency used to clock the DS circuitry is selected to optimize the oscillator rather than having some relationship to the LO frequency. In addition, a single synthesizer may be used in order to simultaneously generate many LO signals.

Abstract: A digital phase lock loop (DPLL) device or system can operate to analyze and estimate a deterministic jitter in the digital domain, while correcting for it in the analog domain. A reference oscillator can provide an analog reference signal to the DPLL via a reference path. A shaper of the reference path can process the analog reference signal and provide a digital signal to a doubler component that doubles the frequency for a digital reference signal. The doubler component itself can add deterministic jitter to the noise of the digital reference signal it provides to the DPLL. An estimation of the DPLL performs various calibration processes to determine the deterministic jitter in the digital domain and provide an analog bias signal to the signal shaper component to correct for the deterministic jitter, keeping it at around zero.

Abstract: Embodiments relate to systems methods and computer readable media to enable a wireless communication device are described. In one embodiment a wireless communication device is configured for phased array communications. The wireless communication device comprises radar circuitry to detect objects that scatter a transmit radiated signal from the wireless communication device. Control circuitry is used to adjust the transmit radiated power of the phased array communications based on information provided by the radar circuitry.

Abstract: A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.

Abstract: A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.

Abstract: Provided is a wound dressing prepared from whole blood that is clotted ex vivo to form a sheet of clotted blood that is applied onto the skin over a sight of skin injury.