Patents by Inventor Ignazio PISELLO

Ignazio PISELLO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210232174
    Abstract: A combinational circuit block has input pins configured to receive input digital signals and output pins configured to provide output digital signals as a function of the input digital signals received. A test input pin receives a test input signal. A test output pin provides a test output signal as a function of the test input signal received. A set of scan registers are selectively coupled to either the combinational circuit block or to one another so as to form a scan chain of scan registers serially coupled between the test input pin and the test output pin. The scan registers in the set of scan registers are clocked by a clock signal. At least one input register is coupled between the test input pin and a first scan register of the scan chain. The at least one input register is clocked by an inverted replica of the clock signal.
    Type: Application
    Filed: January 27, 2021
    Publication date: July 29, 2021
    Applicants: STMicroelectronics S.r.l., STMicroelectronics (Shenzhen) R&D Co. Ltd
    Inventors: Ignazio PISELLO, Yu Yong WANG, Dario ARENA, Qi Yu LIU