Patents by Inventor IK-Joon Chang

IK-Joon Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11144386
    Abstract: A memory controller includes an error correction circuit that converts some bits of first data into parity bits for an error correction operation and generates second data including remaining bits of the first data and the parity bits replaced from the some bits, and a physical layer that transmits the second data instead of the first data to a memory device.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: October 12, 2021
    Assignee: UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITY
    Inventors: Ik Joon Chang, Duy Thanh Nguyen
  • Publication number: 20210223852
    Abstract: An electronic device includes a coding module that determines whether a parameter of an artificial neural network is an outlier, depending on a value of the parameter and compresses the parameter by truncating a first bit of the parameter when the parameter is a non-outlier and truncating a second bit of the parameter when the parameter is the outlier, and a decoding module that decodes a compressed parameter.
    Type: Application
    Filed: February 17, 2020
    Publication date: July 22, 2021
    Applicant: University-Industry Cooperation Group of Kyung Hee University
    Inventors: Ik Joon CHANG, Ho Nguyen DONG, Minhson LE
  • Patent number: 10916291
    Abstract: The provided is a method of controlling a dynamic random-access memory (DRAM) device comprising: storing a plurality of pieces of data consisting of a plurality of bits in a memory in a transposed manner; setting at least one refresh period for each of a plurality of rows constituting the memory; and performing a refresh operation of the memory on the basis of the set refresh period.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: February 9, 2021
    Assignees: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG LEE UNIVERSITY
    Inventors: Hyuk Jae Lee, Hyun Kim, Duy Thanh Nguyen, Bo Yeal Kim, Ik Joon Chang
  • Publication number: 20200381039
    Abstract: The provided is a method of controlling a dynamic random-access memory (DRAM) device comprising: storing a plurality of pieces of data consisting of a plurality of bits in a memory in a transposed manner; setting at least one refresh period for each of a plurality of rows constituting the memory; and performing a refresh operation of the memory on the basis of the set refresh period.
    Type: Application
    Filed: August 13, 2019
    Publication date: December 3, 2020
    Inventors: Hyuk Jae LEE, Hyun KIM, Duy Thanh NGUYEN, Bo Yeal KIM, Ik Joon CHANG
  • Publication number: 20200341840
    Abstract: A memory controller includes an error correction circuit that converts some bits of first data into parity bits for an error correction operation and generates second data including remaining bits of the first data and the parity bits replaced from the some bits, and a physical layer that transmits the second data instead of the first data to a memory device.
    Type: Application
    Filed: October 23, 2019
    Publication date: October 29, 2020
    Applicant: University-Industry Cooperation Group of Kyung Hee University
    Inventors: Ik Joon Chang, Duy Thanh Nguyen
  • Patent number: 10574468
    Abstract: The present invention discloses a chaos nanonet device including a nanonet material having metallic and semiconductive properties dispersed on a substrate and an electrode array composed of a plurality of electrodes that has a selected domain size on the nanonet material, and a PUF security apparatus based on the chaos nanonet device.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: February 25, 2020
    Assignees: UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITY, RESEARCH BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Sun Kook Kim, Ik Joon Chang, Joon Sung Yang
  • Publication number: 20180062864
    Abstract: The present invention discloses a chaos nanonet device including a nanonet material having metallic and semiconductive properties dispersed on a substrate and an electrode array composed of a plurality of electrodes that has a selected domain size on the nanonet material, and a PUF security apparatus based on the chaos nanonet device.
    Type: Application
    Filed: January 6, 2016
    Publication date: March 1, 2018
    Applicants: UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITY, RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Sun Kook KIM, Ik Joon CHANG, Joon Sung YANG, Hyung June LEE
  • Patent number: 9462072
    Abstract: A data transmission method in an ad-hoc network includes: a determining step in which a data sink node determines information of a route from a source node to the data sink node and a kind of data collected by the source node; a selecting step in which the data sink node selects a target node to compress data from the source node and a relay node with respect to the source node to minimize estimated total energy consumption of the network and a kind of a compression algorithm to be used by the target node using the information of the route and the kind of data; an informing step in which the data sink node informs the target node of data compression information including the kind of a compression algorithm depending on the information of the route and the kind of data; and a compressing and transmitting step in which the target node compresses collected or received data according to the data compression information and transmits the data.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: October 4, 2016
    Assignees: EWHA UNIVERSITY-INDUSTRY COLLABORATION, UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITY
    Inventors: HyungJune Lee, Hyun Seok Kim, Ye Lim Youn, Ik Joon Chang
  • Publication number: 20130285696
    Abstract: An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured.
    Type: Application
    Filed: June 27, 2013
    Publication date: October 31, 2013
    Inventors: Lew Chua-Eoan, Boris Andreev, Yuancheng Christopher Pan, Amirali Shayan, Xiaohua Kong, Mikhail Popovich, Mauricio Calle, IK-Joon Chang
  • Patent number: 8497694
    Abstract: An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: July 30, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Lew Chua-Eoan, Boris Andreev, Christopher Phan, Amirali Shayan, Xiaohua Kong, Mikhail Popovich, Mauricio Calle, IK-Joon Chang
  • Publication number: 20110193589
    Abstract: An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured.
    Type: Application
    Filed: February 10, 2010
    Publication date: August 11, 2011
    Applicant: QUALCOMM INCORPORATED
    Inventors: Lew G. Chua-Eoan, Boris Andreev, Christopher Phan, Amirali Shayan, Xiaohua Kong, Mikhail Popovich, Mauricio Calle, IK-Joon Chang