Patents by Inventor Ikuo Magaki
Ikuo Magaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230223083Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.Type: ApplicationFiled: March 14, 2023Publication date: July 13, 2023Applicant: Kioxia CorporationInventors: Hiroshi SUKEGAWA, Ikuo MAGAKI, Tokumasa HARA, Shirou FUJITA
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Patent number: 11631463Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.Type: GrantFiled: July 21, 2021Date of Patent: April 18, 2023Assignee: Kioxia CorporationInventors: Hiroshi Sukegawa, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
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Publication number: 20210350855Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.Type: ApplicationFiled: July 21, 2021Publication date: November 11, 2021Applicant: Toshiba Memory CorporationInventors: Hiroshi SUKEGAWA, Ikuo MAGAKI, Tokumasa HARA, Shirou FUJITA
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Patent number: 11100999Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.Type: GrantFiled: November 23, 2020Date of Patent: August 24, 2021Assignee: Toshiba Memory CorporationInventors: Hiroshi Sukegawa, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
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Publication number: 20210074363Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.Type: ApplicationFiled: November 23, 2020Publication date: March 11, 2021Applicant: Toshiba Memory CorporationInventors: Hiroshi SUKEGAWA, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
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Patent number: 10878913Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.Type: GrantFiled: October 18, 2019Date of Patent: December 29, 2020Assignee: Toshiba Memory CorporationInventors: Hiroshi Sukegawa, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
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Patent number: 10747449Abstract: According to one embodiment, a memory system is provided with a nonvolatile memory, a controller, a volatile memory and an address translation table. The address translation table includes a high level and a plurality of low levels. The high level indicates positions in the nonvolatile memory in which the low levels are recorded. The low levels indicate positions in the nonvolatile memory in which data is recorded. The controller holds the high level of the address translation table in the first area of the volatile memory, and shuts off the supply of power to the second area of the volatile memory based on a transition from a normal-power state to a low-power state.Type: GrantFiled: March 6, 2015Date of Patent: August 18, 2020Assignee: Toshiba Memory CorporationInventors: Tatsuya Zettsu, Katsuhiko Ueki, Yoshihisa Kojima, Hiroshi Yao, Kenichiro Yoshii, Ikuo Magaki
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Patent number: 10490282Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.Type: GrantFiled: July 26, 2018Date of Patent: November 26, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroshi Sukegawa, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
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Publication number: 20180330792Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.Type: ApplicationFiled: July 26, 2018Publication date: November 15, 2018Applicant: Toshiba Memory CorporationInventors: Hiroshi SUKEGAWA, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
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Patent number: 10062438Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.Type: GrantFiled: August 8, 2016Date of Patent: August 28, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroshi Sukegawa, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
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Patent number: 9870170Abstract: According to one embodiment, a memory controller includes a first volatile memory, a second volatile memory, and a controller. The first volatile memory temporarily stores therein data acquired from outside. The controller controls the temporarily stored data to be transferred from the first volatile memory to a non-volatile memory, stores correspondence information of the transferred data to the non-volatile memory in the second volatile memory, and updates correspondence information stored in the non-volatile memory based on the correspondence information stored in the second volatile memory by using the first volatile memory after the data transfer as a work area. The correspondence information represents association between a logical address and a physical address of the data.Type: GrantFiled: February 26, 2016Date of Patent: January 16, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Naoto Oshiyama, Ikuo Magaki, Satoshi Kaburaki, Takashi Ogasawara
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Publication number: 20170199705Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.Type: ApplicationFiled: August 8, 2016Publication date: July 13, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi SUKEGAWA, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
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Publication number: 20170075623Abstract: According to one embodiment, a memory controller includes a first volatile memory, a second volatile memory, and a controller. The first volatile memory temporarily stores therein data acquired from outside. The controller controls the temporarily stored data to be transferred from the first volatile memory to a non-volatile memory, stores correspondence information of the transferred data to the non-volatile memory in the second volatile memory, and updates correspondence information stored in the non-volatile memory based on the correspondence information stored in the second volatile memory by using the first volatile memory after the data transfer as a work area. The correspondence information represents association between a logical address and a physical address of the data.Type: ApplicationFiled: February 26, 2016Publication date: March 16, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Naoto OSHIYAMA, Ikuo Magaki, Satoshi Kaburaki, Takashi Ogasawara
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Patent number: 9431112Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.Type: GrantFiled: March 7, 2014Date of Patent: August 30, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Sukegawa, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
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Publication number: 20160034221Abstract: According to one embodiment, a memory system is provided with a nonvolatile memory, a controller, a volatile memory and an address translation table. The address translation table includes a high level and a plurality of low levels. The high level indicates positions in the nonvolatile memory in which the low levels are recorded. The low levels indicate positions in the nonvolatile memory in which data is recorded. The controller holds the high level of the address translation table in the first area of the volatile memory, and shuts off the supply of power to the second area of the volatile memory based on a transition from a normal-power state to a low-power state.Type: ApplicationFiled: March 6, 2015Publication date: February 4, 2016Inventors: Tatsuya Zettsu, Katsuhiko Ueki, Yoshihisa Kojima, Hiroshi Yao, Kenichiro Yoshii, Ikuo Magaki
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Publication number: 20150206590Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device and a controller. The system includes the nonvolatile semiconductor memory device including a plurality of memory cells; and the controller configured to control one of read operation, write operation, and a use frequency of the read operation or the write operation on the nonvolatile semiconductor memory device, and configured to change controlling for a memory cell belonging to a first group of the memory cells and to change controlling for a memory cell belonging to a second group located on an upper side or a lower side of the memory cell belonging to the first group.Type: ApplicationFiled: August 20, 2014Publication date: July 23, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Haruka SAKUMA, Yoshiaki Fukuzumi, Hideaki Aochi, Hiroshi Sukegawa, Tokumasa Hara, Hiroshi Yao, Shirou Fujita, Ikuo Magaki, Kiwamu Sakuma, Masumi Saitoh
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Patent number: 9003261Abstract: A memory system includes a first nonvolatile memory, a second nonvolatile memory with a longer access latency than the first nonvolatile memory, a first error correction unit, a second error correction unit, and an interface. The first nonvolatile memory stores first data and a first error correction code generated for the first data. The second nonvolatile memory stores a second error correction code which is generated for the first data with a higher correction ability than that of the first error correction code. The first error correction unit performs error correction on the first data by using the first error correction code. The second error correction unit performs error correction on the first data by using the second error correction code. The interface transmits the first data after the error correction to a host.Type: GrantFiled: September 3, 2013Date of Patent: April 7, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Ikuo Magaki, Naoto Oshiyama, Kenichiro Yoshii, Kosuke Hatsuda, Shirou Fujita, Tokumasa Hara, Kohei Oikawa, Kenta Yasufuku
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Publication number: 20150036430Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.Type: ApplicationFiled: March 7, 2014Publication date: February 5, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Sukegawa, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
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Patent number: 8879349Abstract: A storage device according to an embodiment includes first and second non-volatile semiconductor memories. In addition, the storage device includes first controller that controls the first non-volatile memory to cause the first non-volatile memory to perform processes. In addition, the storage device includes second controller that controls the second non-volatile memory to cause the second non-volatile memory to perform processes. The storage device further includes a signal line which is connected to the first controller and the second controller and through which a token is transmitted between the first controller and the second controller. The first controller is capable of controlling the first non-volatile memory while holding the token and the second controller is capable of controlling the second non-volatile memory while holding the token.Type: GrantFiled: August 6, 2013Date of Patent: November 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kenichiro Yoshii, Ikuo Magaki, Naoto Oshiyama, Tokumasa Hara, Akira Yamaga, Ryo Yamaki, Kenta Yasufuku, Naomi Takeda, Yu Nakanishi, Arata Miyamoto, Naoaki Kokubun, Daisuke Iwai
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Publication number: 20140241096Abstract: A storage device according to an embodiment includes first and second non-volatile semiconductor memories. In addition, the storage device includes first controller that controls the first non-volatile memory to cause the first non-volatile memory to perform processes. In addition, the storage device includes second controller that controls the second non-volatile memory to cause the second non-volatile memory to perform processes. The storage device further includes a signal line which is connected to the first controller and the second controller and through which a token is transmitted between the first controller and the second controller. The first controller is capable of controlling the first non-volatile memory while holding the token and the second controller is capable of controlling the second non-volatile memory while holding the token.Type: ApplicationFiled: August 6, 2013Publication date: August 28, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Kenichiro YOSHII, Ikuo MAGAKI, Naoto OSHIYAMA, Tokumasa HARA, Akira YAMAGA, Ryo YAMAKI, Kenta YASUFUKU, Naomi TAKEDA, Yu NAKANISHI, Arata MIYAMOTO, Naoaki KOKUBUN, Daisuke IWAI