Patents by Inventor Ikuo Matsunaga

Ikuo Matsunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10928661
    Abstract: A display device includes a base film including a first region and a plurality of second regions having the first region therebetween; an inorganic insulating film on the base film, the inorganic insulating film being in contact with the plurality of second regions of the base film; a plurality of first pixels overlapping the first region; and a plurality of second pixels overlapping the plurality of second regions with the inorganic insulating film being between the plurality of second pixels and the plurality of second regions. The inorganic insulating film is divided by the first region and is discontinuous between the plurality of second regions.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: February 23, 2021
    Assignee: Japan Display Inc.
    Inventor: Ikuo Matsunaga
  • Publication number: 20200209670
    Abstract: A display device includes a base film including a first region and a plurality of second regions having the first region therebetween; an inorganic insulating film on the base film, the inorganic insulating film being in contact with the plurality of second regions of the base film; a plurality of first pixels overlapping the first region; and a plurality of second pixels overlapping the plurality of second regions with the inorganic insulating film being between the plurality of second pixels and the plurality of second regions. The inorganic insulating film is divided by the first region and is discontinuous between the plurality of second regions.
    Type: Application
    Filed: March 9, 2020
    Publication date: July 2, 2020
    Inventor: Ikuo MATSUNAGA
  • Patent number: 10620464
    Abstract: A display device includes a base film including a first region and a plurality of second regions having the first region therebetween; an inorganic insulating film on the base film, the inorganic insulating film being in contact with the plurality of second regions of the base film; a plurality of first pixels overlapping the first region; and a plurality of second pixels overlapping the plurality of second regions with the inorganic insulating film being between the plurality of second pixels and the plurality of second regions. The inorganic insulating film is divided by the first region and is discontinuous between the plurality of second regions.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: April 14, 2020
    Assignee: Japan Display Inc.
    Inventor: Ikuo Matsunaga
  • Patent number: 10026786
    Abstract: A display device comprising a display region on which a plurality of subpixels are arranged. The plurality of subpixels respectively comprise a transistor, a first organic insulating film, an inorganic insulating film, an electrode, and a second organic insulating film that covers an edge part of a first region in which a pattern of the electrode is formed. The inorganic film comprises an opening in a region that overlaps with the second region in which a pattern of the electrode is not formed in a planar view. The opening is formed in a middle between the first region of a first subpixel and the first region of a second subpixel or at a point located on the side closer to the first subpixel between the first region of the first subpixel and the first region of the second subpixel.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: July 17, 2018
    Assignee: Japan Display Inc.
    Inventors: Ikuo Matsunaga, Kenta Kajiyama
  • Publication number: 20180136508
    Abstract: A display device includes a base film including a first region and a plurality of second regions having the first region therebetween; an inorganic insulating film on the base film, the inorganic insulating film being in contact with the plurality of second regions of the base film; a plurality of first pixels overlapping the first region; and a plurality of second pixels overlapping the plurality of second regions with the inorganic insulating film being between the plurality of second pixels and the plurality of second regions. The inorganic insulating film is divided by the first region and is discontinuous between the plurality of second regions.
    Type: Application
    Filed: October 25, 2017
    Publication date: May 17, 2018
    Inventor: Ikuo MATSUNAGA
  • Publication number: 20170236882
    Abstract: A display device comprising a display region on which a plurality of subpixels are arranged. The plurality of subpixels respectively comprise a transistor, a first organic insulating film, an inorganic insulating film, an electrode, and a second organic insulating film that covers an edge part of a first region in which a pattern of the electrode is formed. The inorganic film comprises an opening in a region that overlaps with the second region in which a pattern of the electrode is not formed in a planar view. The opening is formed in a middle between the first region of a first subpixel and the first region of a second subpixel or at a point located on the side closer to the first subpixel between the first region of the first subpixel and the first region of the second subpixel.
    Type: Application
    Filed: January 12, 2017
    Publication date: August 17, 2017
    Applicant: Japan Display Inc.
    Inventors: Ikuo MATSUNAGA, Kenta KAJIYAMA
  • Publication number: 20170207287
    Abstract: A display device in an embodiment according to the present invention includes a conductive layer over an interlayer insulating layer, a pixel electrode over the conductive layer, and an insulating layer provided between the conductive layer and the pixel electrode. The pixel electrode is electrically connected to a transistor via a contact hole through the insulating layer and the interlayer insulating layer, the conductive layer has an opening having the contact hole inside and spreading to an outer region outside of the pixel electrode, the opening has an open end, and one side of the opening bends in the outer region outside of the pixel electrode.
    Type: Application
    Filed: October 26, 2016
    Publication date: July 20, 2017
    Inventors: Ikuo MATSUNAGA, Kenta KAJIYAMA
  • Patent number: 7645631
    Abstract: There is provided a method of manufacturing an organic EL display including an insulating substrate, a power supply terminal, a plurality of pixels arrayed on the substrate and each including an organic EL element and a pixel circuit, and an organic planarizing film covering the pixel circuits and interposed between the organic EL elements and the substrate, including selecting a pixel which can be recognized as a dark spot and/or a bright spot from the pixels, and irradiating, of the pixel circuit included in the selected pixel, a portion located between the organic planarizing film and the substrate with an energy beam through the substrate to electrically disconnect the organic EL element included in the selected pixel from the power supply terminal.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: January 12, 2010
    Assignee: Toshiba Matsushita Display Technology Co., Ltd.
    Inventor: Ikuo Matsunaga
  • Publication number: 20070195217
    Abstract: An intermediate portion of a low voltage power supply wire is extinguished by irradiation of a laser beam to form a wire cut portion. A different potential portion serves as the wire cut portion of the low voltage power supply wire. The distance between the end portions of a high voltage power supply wire and the low voltage power supply wire between which the potential is different is increased. An electrical short-circuit between the high voltage power supply wire and the low voltage power supply wire hardly occurs. Even when impurities invade into the gap between an insulating layer on the high voltage power supply wire and the low voltage power supply wire and a glass substrate, electrode corrosion of the high voltage power supply wire and the low voltage power supply wire can be prevented. A display failure can be prevented.
    Type: Application
    Filed: January 16, 2007
    Publication date: August 23, 2007
    Inventors: Kiyoshi Miyashita, Ikuo Matsunaga, Masashi Ishimaru, Yoshihito Nakawaga, Masaki Seto, Jun Hanari
  • Publication number: 20050269962
    Abstract: There is provided a method of manufacturing an organic EL display including an insulating substrate, a power supply terminal, a plurality of pixels arrayed on the substrate and each including an organic EL element and a pixel circuit, and an organic planarizing film covering the pixel circuits and interposed between the organic EL elements and the substrate, including selecting a pixel which can be recognized as a dark spot and/or a bright spot from the pixels, and irradiating, of the pixel circuit included in the selected pixel, a portion located between the organic planarizing film and the substrate with an energy beam through the substrate to electrically disconnect the organic EL element included in the selected pixel from the power supply terminal.
    Type: Application
    Filed: July 27, 2005
    Publication date: December 8, 2005
    Applicant: Toshiba Matsushita Display Technology Co., Ltd
    Inventor: Ikuo Matsunaga
  • Patent number: 6873174
    Abstract: A first signal line and a second signal line are paired, and in one signal line selection period, CPU of the inspection circuit controls a write circuit and writes analog signals into the first signal line selected by means of a switch of the selection circuit. In the next signal line selection period, CPU controls a read circuit and reads output signals from the second signal line selected by means of the switch. CPU detects a short circuit between the paired signal lines based upon the output signals from the second signal line.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: March 29, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ikuo Matsunaga, Ryoichi Watanabe, Masahiro Seiki
  • Publication number: 20030184334
    Abstract: A first signal line and a second signal line are paired, and in one signal line selection period, CPU of the inspection circuit controls a write circuit and writes analog signals into the first signal line selected by means of a switch of the selection circuit. In the next signal line selection period, CPU controls a read circuit and reads output signals from the second signal line selected by means of the switch. CPU detects a short circuit between the paired signal lines based upon the output signals from the second signal line.
    Type: Application
    Filed: January 4, 2001
    Publication date: October 2, 2003
    Inventors: Ikuo Matsunaga, Ryoichi Watanabe, Masahiro Seiki