Patents by Inventor Ikuro Masuda
Ikuro Masuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5696715Abstract: A semiconductor integrated circuit memory device has at least two logic blocks, each logic block including at least two logic units and each logic unit having a number of metal oxide semiconductor field effect transistors (MOS FET's) integrated therein. Bipolar transistors for driving the MOS FET's are selectively arranged between the logic blocks and/or the logic units so as to shorten a critical path of a logic block. The memory device may include a word driver circuit having a bipolar transistor connected to MOSFETs in an address decoder and memory cells of the memory device. The memory device may also include a sense circuit having a bipolar transistor for high speed discharge of a bit line, as well as an output buffer including a bipolar transistor for reducing signal transmission delays in driving a bus.Type: GrantFiled: February 13, 1995Date of Patent: December 9, 1997Assignee: Hitachi, Ltd.Inventors: Hideo Maejima, Ikuro Masuda
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Patent number: 5644548Abstract: A dynamic random access memory device is provided having a dynamic memory cell, a word line coupled to the dynamic memory cell, a data line coupled to the dynamic memory cell, a precharge circuit coupled to the data line, a word driver coupled to the word line and a decoder coupled to the word driver. A plurality of address lines coupled to the decoder. The decoder has a first logic circuit whose inputs are connected to the plurality of address lines. The decoder also has a latch circuit whose input is connected to an output of the first logic circuit and whose output is connected to the word line.Type: GrantFiled: August 27, 1996Date of Patent: July 1, 1997Assignee: Hitachi, Ltd.Inventors: Goro Kitsukawa, Takao Watanabe, Ryoichi Hori, Noriyuki Honma, Kunihiko Yamaguchi, Kiyoo Ito, Masahiro Iwamura, Ikuro Masuda
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Patent number: 5600268Abstract: A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.Type: GrantFiled: September 30, 1994Date of Patent: February 4, 1997Assignee: Hitachi, Ltd.Inventors: Ikuro Masuda, Kazuo Kato, Takao Sasayama, Yoji Nishio, Shigeo Kuboki, Masahiro Iwamura
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Patent number: 5512847Abstract: In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS--TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.Type: GrantFiled: October 6, 1994Date of Patent: April 30, 1996Assignee: Hitachi, Ltd.Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akira Uragami, Masayoshi Yoshimura, Toshiaki Matsubara
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Patent number: 5495183Abstract: In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS--TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.Type: GrantFiled: May 12, 1995Date of Patent: February 27, 1996Assignee: Hitachi, Ltd.Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akira Urragami, Masayoshi Yoshimura, Toshiaki Matsubara
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Patent number: 5455955Abstract: A data processing system incorporating a main memory for storing instructions and operands and performing data processing in a mode of microprogram control system in response to instructions read out of the main memory. The system translates an instruction word read out of the main memory into an intermediate machine word having the orthogonal format, and addresses a microprogram memory in correspondence to the instruction word by analyzing the intermediate machine word. The system further incorporates a plurality of register sets so that each different task can use an individual register set, and a memory for memorizing the number of registers holding parameters used commonly among procedures corresponding to the register sets, so that the number of registers for each use can be changed arbitrarily for each register set by using the memory.Type: GrantFiled: September 28, 1992Date of Patent: October 3, 1995Assignee: Hitachi, Ltd.Inventors: Hiroyuki Kida, Hideo Maejima, Ikuro Masuda, Shirou Baba
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Patent number: 5378941Abstract: A high speed and low power consumption semiconductor integrated circuit device has a plurality of internal circuits each including circuit elements for performing a desired circuit operation, a plurality of input circuits for receiving external input signals and supplying the signals to the internal circuits and a plurality of output circuits for receiving the output signals from the internal circuits and supplying signals to an external circuit. Each of the internal circuits is primarily constructed by bipolar transistors and MOS transistors, and at least one of each of the input circuits and each of the output circuits is primarily constructed by bipolar transistors.Type: GrantFiled: November 30, 1992Date of Patent: January 3, 1995Assignee: Hitachi, Ltd.Inventors: Yoji Nishio, Ikuro Masuda, Kazuo Kato, Shigeo Kuboki, Masahiro Iwamura
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Patent number: 5371713Abstract: In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.Type: GrantFiled: March 9, 1994Date of Patent: December 6, 1994Assignee: Hitachi, Ltd.Inventors: Katsumi Ogiue, Yukio Suzuki, Ikuro Masuda, Masanori Odaka, Hideaki Uchida
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Patent number: 5333282Abstract: In a semiconductor integrated circuit device having at least two logic blocks each including at least two logic units each having a number of MOS FET's integrated therein, bipolar transistors for driving the MOS FET's are selectively arranged between the logic blocks and/or the logic units so as to shorten the critical path of a logic block.Type: GrantFiled: October 8, 1991Date of Patent: July 26, 1994Assignee: Hitachi, Ltd.Inventors: Hideo Maejima, Ikuro Masuda
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Patent number: 5311482Abstract: In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.Type: GrantFiled: July 16, 1993Date of Patent: May 10, 1994Assignee: Hitachi, Ltd.Inventors: Katsumi Ogiue, Yukio Suzuki, Ikuro Masuda, Masanori Odaka, Hideaki Uchida
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Patent number: 5245224Abstract: In an input level converter for TTL-CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS-TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.Type: GrantFiled: March 3, 1992Date of Patent: September 14, 1993Assignee: Hitachi, Ltd.Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akira Uragami, Masayoshi Yoshimura, Toshiaki Matsubara
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Gate circuit of combined field-effect and bipolar transistors with an improved discharge arrangement
Patent number: 5239212Abstract: A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.Type: GrantFiled: December 8, 1992Date of Patent: August 24, 1993Assignee: Hitachi, Ltd.Inventors: Ikuro Masuda, Kazuo Kato, Takao Sasayama, Yoji Nishio, Shigeo Kuboki, Masahiro Iwamura -
Patent number: 5153452Abstract: There are provided a bipolar-MOS IC device smaller than half-micron scale, and a combination of such IC device and external circuits. The IC device has an internal voltage generating circuit for generating an internal power source by using an external power source, the voltage of the internal power source being lower than that of the external power source. The internal voltage generating circuit includes an NPN transistor formed in an N-type region or N-type island within a P-type semiconductor substrate of the IC device, and a PMOS transistor formed in the N-type island. The collector of the NPN transistor and the source of the PMOS transistor are used as external power source terminals. The drain of the PMOS transistor is connected to the base of the NPN transistor. The gate is used as a control signal terminal. The emitter of the NPN transistor is used as an internal power source output terminal.Type: GrantFiled: August 30, 1989Date of Patent: October 6, 1992Assignee: Hitachi Ltd.Inventors: Masahiro Iwamura, Shigeya Tanaka, Tatsumi Yamauchi, Ikuro Masuda, Tetsuo Nakano
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Patent number: 5117382Abstract: A semiconductor integrated circuit is provided for performing an arithmetic operation using an arithmetic operation circuit. The integrated circuit includes a read bus for connecting the arithmetic operation circuit with a plurality of registers which store input data and/or output data of said arithmetic operation circuit. A precharge and sense circuit connects said arithmetic operation circuit to said read bus. The precharge and sense circuit includes a precharge circuit to precharge the read bus to a first level before the read operation, and a sense circuit to detect that the level of the read bus has discharged to a second, lower level after the read operation begins. In this way, the integrated circuit can detect very slight potential variations on said read bus.Type: GrantFiled: November 26, 1990Date of Patent: May 26, 1992Assignee: Hitachi, Ltd.Inventors: Hideo Maejima, Takashi Hotta, Ikuro Masuda, Masahiro Iwamura, Kouzaburou Kurita, Masahiro Ueno
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Patent number: 5103120Abstract: In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.Type: GrantFiled: January 2, 1991Date of Patent: April 7, 1992Assignee: Hitachi, Ltd.Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akira Uragami, Masayoshi Yoshimura, Toshiaki Matsubara
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Patent number: 5042010Abstract: In order to provide high speed and lower power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portiosn of the circuit use CMOS elements of lower power consumption. This arrangement is particulary advantageous in memory circuits.Type: GrantFiled: May 8, 1990Date of Patent: August 20, 1991Assignee: Hitachi, Ltd.Inventors: Katsumi Ogiue, Yukio Suzuki, Ikuro Masuda, Masanori Odaka, Hideaki Uchida
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Patent number: 5005153Abstract: In a semiconductor integrated circuit device having at least two logic blocks each including at least two logic units each having a number of MOS FET's integrated therein, bipolar transistors for driving the MOS FET's are selectively arranged between the logic blocks and/or the logic units so as to shorten the critical path of a logic block.Type: GrantFiled: February 12, 1988Date of Patent: April 2, 1991Assignee: Hitachi, Ltd.Inventors: Hideo Maejima, Ikuro Masuda
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Patent number: 5001366Abstract: A high-speed operation, low-space consumption gate circuit structure-comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.Type: GrantFiled: December 1, 1987Date of Patent: March 19, 1991Assignee: Hitachi, Ltd.Inventors: Ikuro Masuda, Kazuo Kato, Takao Sasayama, Yoji Nishio, Shigeo Kuboki
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Patent number: 4983862Abstract: In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.Type: GrantFiled: October 31, 1989Date of Patent: January 8, 1991Assignee: Hitachi, Ltd.Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akira Uragami, Masayoshi Yoshimura, Toshiaki Matsubara
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Patent number: 4924439Abstract: In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.Type: GrantFiled: May 30, 1989Date of Patent: May 8, 1990Assignee: Hitachi, Ltd.Inventors: Katsumi Ogiue, Yukio Suzuki, Ikuro Masuda, Masanori Odaka, Hideaki Uchida