Patents by Inventor Ikuro Masuda

Ikuro Masuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4890017
    Abstract: A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.
    Type: Grant
    Filed: December 1, 1987
    Date of Patent: December 26, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Ikuro Masuda, Kazuo Kato, Takao Sasayama, Yoji Nishio, Shigeo Kuboki, Masahiro Iwamura
  • Patent number: 4879480
    Abstract: In an input level converter for TTL - CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS - TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
    Type: Grant
    Filed: September 2, 1988
    Date of Patent: November 7, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akiro Uragami, Masayoshi Yoshimura, Toshiaki Matsubara
  • Patent number: 4860148
    Abstract: A semiconductor integrated circuit device is provided with an input and/or an output terminal and at least one semiconductor device. The circuit has a resistor provided between the input terminal and/or the output terminal and one of the at least one semiconductor devices and an electronic switch connected in parallel with the resistor. The electronic switch is on-off controlled so as to exhibit a relatively low impedance when the semiconductor device is in operation and a relatively high impedance when the semiconductor device is not in operation. Thus, the semiconductor integrated circuit device is operable at a higher speed with an improved reliability and/or with controllable response characteristics, as compared with the conventional device.
    Type: Grant
    Filed: April 13, 1987
    Date of Patent: August 22, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Iwamura, Ikuro Masuda, Hideaki Uchida
  • Patent number: 4858189
    Abstract: In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.
    Type: Grant
    Filed: November 17, 1987
    Date of Patent: August 15, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Katsumi Ogiue, Yukio Suzuki, Ikuro Masuda, Masanori Odaka, Hideaki Uchida
  • Patent number: 4853560
    Abstract: When a counter-part power supply designator of a first LSI designates that the counter-part power supply voltage of another LSI is a first power supply difference which is the same as the power supply difference of its own, an output circuit control controls an output circuit and the output circuit produces an output signal having a level adaptive to the counter-part LSI operating at the first power supply voltage. When the counter-part power supply voltage designator designates that the counter-part power supply voltage difference, lower than the first power supply voltage difference, the output circuit control controls the output circuit and the output circuit produces an output signal having a level adaptive to the counter-part LSI operating at the second power supply voltage difference. Thus, a plurality of LSIs can be operated at mutually different power supply voltages.
    Type: Grant
    Filed: January 27, 1988
    Date of Patent: August 1, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Iwamura, Hideo Maejima, Ikuro Masuda
  • Patent number: 4829201
    Abstract: A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.
    Type: Grant
    Filed: December 1, 1987
    Date of Patent: May 9, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Ikuro Masuda, Kazuo Kato, Takao Sasayama, Yoji Nishio, Shigeo Kuboki, Masahiro Iwamura
  • Patent number: 4813020
    Abstract: A composite circuit including a MOS transistor and a bipolar transistor to be driven by the MOS transistors and forming an output stage, a logical inverter circuit connected to an output terminal of the composite circuit to invert the level of the output signal, and a MOS transistor having a source and a drain thereof parallelly connected across a collector and an emitter of the bipolar transistor are provided. When the bipolar transistor conducts with a voltage drop associated with a base-emitter voltage, the parallelly connected MOS transistor renders the bipolar transistor completely conductive so that a level-shiftless output signal is produced.
    Type: Grant
    Filed: March 17, 1988
    Date of Patent: March 14, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Iwamura, Ikuro Masuda
  • Patent number: 4808850
    Abstract: A novel composite circuit comprises a first bipolar transistor with a collector of a first conductivity type connected to a first potential, an emitter of the first conductivity type connected to an output, a second bipolar transistor with a collector of the first conductivity type connected to the output and an emitter of the first conductivity type connected to a second potential, a field effect transistor of a second conductivity type with a gate connected to an input, a source connected to a third potential and a drain connected to the base of the first bipolar transistor, a field effect transistor of the first conductivity type with a gate connected to the input, a drain connected to the base of the first bipolar transistor, and a source connected to the base of the second bipolar transistor, and a unidirectional element inserted between the output and the drain of the field effect transistor of the first conductivity type and having a direction of rectification opposite to that of the PN junction formed
    Type: Grant
    Filed: January 2, 1987
    Date of Patent: February 28, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Ikuro Masuda, Masahiro Iwamura, Motohisa Nishihara
  • Patent number: 4801983
    Abstract: A unidirectional switching circuit having no charge storage effect for performing a high-speed switching operation is disclosed in which one of the anode and cathode terminals of a Schottky-barrier diode is connected to one of the source and drain terminals of a field effect transistor to form the series combination of the Schottky-barrier diode and the field effect transistor, that one of end terminals of the series combination which exists on the anode side of the diode, is used as an input terminal, the other end terminal existing on the cathode side is used as an output terminal, the gate electrode of the field effect transistor is used as a switching control electrode, and a current flowing through the switching circuit in a direction from the input terminal to the output terminal is controlled in accordance with a signal applied to the switching control electrode.
    Type: Grant
    Filed: August 22, 1986
    Date of Patent: January 31, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Ueno, Masahiro Iwamura, Kozaburo Kurita, Ikuro Masuda
  • Patent number: 4797583
    Abstract: A level converter for transforming differential input voltages into an output voltage comprises a voltage-current conversion circuit for transforming the differential input voltages into differential currents, a current detection circuit for detecting the differential currents, a current amplifying circuit for amplifying the differential currents in response to the output of the current detection circuit, and a current-voltage conversion circuit for transforming the amplified differential currents into an output voltage, thereby allowing fast operation and drastic level conversion.
    Type: Grant
    Filed: December 19, 1984
    Date of Patent: January 10, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Ueno, Kozaburo Kurita, Ikuro Masuda, Nobuaki Miyakawa
  • Patent number: 4789958
    Abstract: A carry-look-ahead adder is provided which is implemented as a semiconductor integrated circuit. The integrated circuit includes a bipolar transistor coupled to the output terminal for providing an output indicative of the arithmetic operation. Impedance elements are coupled to the bipolar transistor and at least one FET is provided to control the on/off state of the bipolar transistor.
    Type: Grant
    Filed: February 19, 1985
    Date of Patent: December 6, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Maejima, Takashi Hotta, Ikuro Masuda, Masahiro Iwamura, Kouzaburou Kurita, Masahiro Ueno
  • Patent number: 4769561
    Abstract: A bipolar transistor-complementary field effect transistor composite circuit is provided which includes a pair of first and second bipolar transistors each having a collector of a first conductivity type, a base of a second conductivity type and an emitter of a first conductivity type. Collector-emitter current paths of the bipolar transistors are connected in series to each other between first and second potentials, with a connection node providing an output of the composite circuit. Field effect transistors are respectively coupled between the bases and collectors of the bipolar transistors for controlling the on-off states of the bipolar transistors in opposite relationship to one another in response to an input signal provided to the composite circuit. Also, discharge arrangements are provided for the bases of the first and second bipolar transistors to discharge parasitic capacitance in the bases of the first and second bipolar transistors when they are turned off.
    Type: Grant
    Filed: December 11, 1984
    Date of Patent: September 6, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Iwamura, Ikuro Masuda
  • Patent number: 4727517
    Abstract: A semiconductor memory is provided including a plurality of row lines, memory cells driven by selecting a row line, sense amplifiers connected to the memory cells via column lines, and a column line voltage setting circuit for setting a predetermined voltage on the column lines. The predetermined voltage is defined by a voltage necessary to activate semiconductor switch elements constituting the column line voltage setting circuit, and is made nearly equal to the threshold voltage of the sense amplifiers. Thus, a high-speed, low power consumption semiconductor memory can be realized.
    Type: Grant
    Filed: October 9, 1985
    Date of Patent: February 23, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Ueno, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Ikuro Masuda, Tetsuo Nakano
  • Patent number: 4719373
    Abstract: A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.
    Type: Grant
    Filed: April 30, 1987
    Date of Patent: January 12, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Ikuro Masuda, Kazuo Kato, Takao Sasayama, Yoji Nishio, Shigeo Kuboki, Masahiro Iwamura
  • Patent number: 4713796
    Abstract: In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.
    Type: Grant
    Filed: February 13, 1985
    Date of Patent: December 15, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Katsumi Ogiue, Yukio Suzuki, Ikuro Masuda, Masanori Odaka, Hideaki Uchida
  • Patent number: 4701922
    Abstract: An integrated circuit device comprises combinational circuits and sequential circuits. Each of the sequential circuits is provided with a (common) input control signal terminal for controlling the entry of main input terminal signals into the sequential circuit, a test data input/output terminal, a read/write signal terminal for controlling the transfer of the test data, and a latch circuit. The integrated circuit device is partitioned into sequential circuit groups, and combinational circuit groups used as partitioning test units, the main input/output terminal groups of which are connected with the sequential circuit groups through wiring layers. Test data are written into and read out from the sequential circuit groups under control of read/write signal lines through bus lines dedicated to testing. Thus, a higher fault-coverage ratio can be easily obtained with a smaller number of steps and a small test circuit area.
    Type: Grant
    Filed: August 26, 1985
    Date of Patent: October 20, 1987
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Shigeo Kuboki, Ikuro Masuda, Toshiaki Masuda, Terumine Hayashi
  • Patent number: 4694203
    Abstract: A bipolar/CMOS mixed type switching circuit comprising two npn-type bipolar transistors Q.sub.1, Q.sub.2 that are connected in the form of a totem pole in the output stage, a CMOS inverter and an NMOSFET M.sub.3 for driving these transistors in a complementary manner, and resistance means R for discharging the electric charge stored in the base of the transistor Q.sub.2. The threshold voltage of an NMOSFET M.sub.2 constituting the CMOS inverter in the absence of substrate effect is set to be substantially equal to the threshold voltage of the NMOSFET M.sub.3 in the absence of the substrate effect, and the channel conductance W.sub.N /L.sub.N of the NMOSFET M.sub.3 is so set that the threshold voltage V.sub.LT1 of the CMOS inverter and the practical threshold voltage V.sub.LT2 of the NMOSFET M.sub.3 will be nearly the same. Owing to the above structure, there is obtained a switching circuit which permits little through current to flow and which operates at high speeds.
    Type: Grant
    Filed: March 26, 1985
    Date of Patent: September 15, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Akira Uragami, Yukio Suzuki, Masahiro Iwamura, Ikuro Masuda
  • Patent number: 4694202
    Abstract: An improved buffer circuit is provided having an output stage for driving a load and a driver stage for driving said output stage. The output stage is constituted by a first MOS transistor to avoid problems found in bipolar output transistors which result from the amplitude of the output stage being influenced by the voltage V.sub.be of such output bipolar transistors. The driver stage, on the other hand, is formed of a bipolar transistor-MOS transistor composite logic cirucit. This driver stage includes an output circuit having a bipolar transistor for driving said first MOS transistor, and an input circuit including a second MOS transistor responsive to a predetermined input for rendering said bipolar transistor in the on or off state. The channel size of said first MOS transistor is larger than that of said second MOS transistor to give a device having an improved high operating speed.
    Type: Grant
    Filed: December 17, 1984
    Date of Patent: September 15, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Iwamura, Ikuro Masuda
  • Patent number: 4689503
    Abstract: In an input level converter for TTL-CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS-TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
    Type: Grant
    Filed: January 31, 1984
    Date of Patent: August 25, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akira Uragami, Masayoshi Yoshimura, Toshiaki Matsubara
  • Patent number: 4678943
    Abstract: A switching circuit comprises a pre-stage circuit coupled to receive an input signal and an output stage, wherein an output signal having a phase opposite to that of a signal of an input terminal IN can be obtained from an output terminal OUT of the output stage. The pre-stage circuit includes a p-channel MOSFET M1 and an n-channel MOSFET M2 that receive input signals at their gates. The output stage includes two NPN transistors Q1 and Q2 that are connected in series. The drain output of the p-channel MOSFET M1 is applied to the base of one of the transistors of the output stage, and the source output of the n-channel MOSFET M2 is applied to the base of the other of the transistors of the output stage. A third MOSFET M3 is coupled between a power supply and the p-channel MOSFET M1 and the n-channel MOSFET M2. When the MOSFET M3 is rendered non-conductive by a control signal EN, both MOSFETs M1 and M2 and both NPN transistors Q1 and Q2 become non-conductive irrespective of the signal of the input terminal IN.
    Type: Grant
    Filed: February 22, 1985
    Date of Patent: July 7, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Akira Uragami, Yukio Suzuki, Shinji Kadono, Masahiro Iwamura, Ikuro Masuda, Tatsumi Yamauchi